System for receiving burst width greater than cache width by sto

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

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Details

395855, 395872, 711118, 711123, 711138, G06F 1300

Patent

active

058600272

ABSTRACT:
A data processing device includes a data processing core (43), a cache (33) connected to the core and having a cache width, and a bus (31) for receiving from an information source external to the data processing device a burst of information having a width which exceeds the cache width by a width difference. The cache is coupled to the bus to receive and store a first portion of the burst which is equal in width to the cache width. A storage circuit (35) is coupled to the bus to receive and store a second portion of the burst corresponding to the width difference, and the storage circuit has an output coupled to the core.

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