System for providing real-time code coverage

Details System for providing real-time code coverage System for providing real-time code coverage

1998-03-10

1999-10-19

Palys, Joseph E.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714 45, 714 32, G06F 1120

Patent

active

059681888

ABSTRACT:
A system which provides real-time code coverage data on a memory monitored by the system, the code coverage data providing information regarding accesses to the monitored memory, the monitored memory being connected to address lines and data lines, the system comprising: a code coverage memory, the code coverage memory having address inputs and data inputs, wherein signals on the address lines connected to the monitored memory are received at the address inputs of said code coverage memory; and a code coverage control circuit for providing predetermined code coverage data to the data inputs of the code coverage memory. In a preferred embodiment, the code coverage memory is comprised of multiple locations, each of the locations having a predetermined width, and where the code coverage control circuit is adapted to provide predetermined code coverage data in real-time concurrently with the accesses to the monitored memory. The code coverage data is comprised of predetermined bit patterns providing information on the accesses to the monitored memory, where the predetermined bit patterns may be varied for different tests run through the monitored memory. Additionally, in a preferred embodiment, the system is further comprised of: a trace memory, where the trace memory has address inputs and data inputs, and wherein signals on the address lines connected to the monitored memory are received at the data inputs of the code coverage memory for storage in the trace memory; and a trace control circuit in electrical communication with the address inputs of the trace memory, wherein the trace control circuit is adapted to output signals to the address inputs of the trace memory to change the location in the trace memory to which the signals on the address lines connected to the monitored memory are stored.

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