System for providing high performance speculative processing of

Electrical computers and digital processing systems: processing – Processing control – Processing sequence control

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712245, 712246, 712247, G06F 938

Patent

active

060353945

ABSTRACT:
One aspect of the invention relates to a method for operating a superscalar processor having an instruction cache, a sequencing unit, a load/store unit, a cache, an architectural register file and a rename register file. In one particular version of the invention, the method includes the steps of forwarding an instruction from the instruction cache to the sequencing unit operable to access multiple architectural registers; generating a plurality of primitive instructions responsive to the forwarded instruction in which an individual primitive instruction is operable to access an individual architectural register; and sequentially issuing the primitive instructions to move data between the data cache and the rename register file.

REFERENCES:
patent: 5291586 (1994-03-01), Jen
patent: 5416911 (1995-05-01), Dinkjian
patent: 5664215 (1997-09-01), Burgess
patent: 5826084 (1998-10-01), Brooks

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