System for providing a slow command decode over an untrained...

Details System for providing a slow command decode over an untrained... System for providing a slow command decode over an untrained...

2007-06-22

2009-11-24

Lane, Jack A (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S105000, C710S005000, C710S058000, C710S060000

Reexamination Certificate

active

07624244

ABSTRACT:
A memory system for providing a slow command decode over an untrained high-speed interface. The memory system includes a memory system having a memory interface device, an untrained high-speed interface, and a memory controller. The untrained high-speed interface is in communication with the memory interface device. The memory controller generates slow commands and transmits the slow commands to the memory interface device via the untrained high-speed interface. The slow commands operate at a first data rate that is slower than a second data rate utilized by the high-speed interface after it has been trained. The memory interface device receives the slow commands via the untrained high-speed interface, decodes the slow commands, and executes the slow commands.

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