System for providing a host computer with access to a memory on

Details System for providing a host computer with access to a memory on System for providing a host computer with access to a memory on

1995-06-07

1998-12-01

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

39575003, 39575004, 39575005, 711115, 364707, 365227, G06F 132

Patent

active

058451390

ABSTRACT:
A wake-up system is provided to allow host computer access to a Card Information Structure (CIS) on a PCMCIA card during a SLEEP mode. The CIS is stored in a non-volatile memory accessible to a host computer via a PCMCIA bus and to PCMCIA card logic via a local bus. Arbitration logic is coupled between the PCMCIA and local buses to control access to the memory. Sleep logic prevents a fast clock signal from being supplied to the arbitration logic and the PCMCIA card logic when the PCMCIA card is switched into the SLEEP mode. A CIS read detect circuit decodes a CIS read operation on the PCMCIA bus and asserts the CIS detect signal supplied to the sleep logic. In response, the sleep logic allows the fast clock signals to be supplied to the arbitration logic and adapter card subsystem to exit from the SLEEP mode and provide the host computer with access to the memory storing the CIS information.

REFERENCES:
patent: 4385369 (1983-05-01), Sheppard
patent: 5361364 (1994-11-01), Nagashige et al.
patent: 5404543 (1995-04-01), Faucher et al.
patent: 5465367 (1995-11-01), Reddy et al.
patent: 5475847 (1995-12-01), Ikeda
patent: 5546590 (1996-08-01), Pierce
patent: 5584031 (1996-12-01), Burch et al.
patent: 5586332 (1996-12-01), Jain et al.
patent: 5652895 (1997-07-01), Poisner
patent: 5721935 (1998-02-01), DeSchepper et al.
"IBM Technical Disclosure Bulletin", Mar. 1995, vol. 38, pp. 593-596.

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