Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2011-07-19
2011-07-19
Thomas, Shane M (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711SE12093
Reexamination Certificate
active
07984257
ABSTRACT:
A system for protecting supervisor mode data from user code having a processor which implements a register window architecture supporting as separate window stacks for supervisor and user modes with a transition window in one of the window stacks set with at least one invalid window bit in an invalid window mask of the architecture additional to an invalid window bit set for a reserved window of the invalid window mask for transitioning from the supervisor mode to the user mode, supervisor mode-only memory storing the supervisor mode window stack, and user mode accessible memory storing the supervisor and user mode window stacks.
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The SPARC Architecture Manual Version 8, Revision SAV080S19308, SPARC International Inc. 1992.
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Funk David William
Gauke Barry
Fishburn John P
Silverbrook Research Pty Ltd
Thomas Shane M
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