Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data...
Reexamination Certificate
2000-03-30
2003-09-16
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Clock control of data processing system, component, or data...
C713S401000, C365S193000
Reexamination Certificate
active
06622256
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the field of signal transfer between components, and more specifically to a strobe glitch protection mechanism for a source synchronous I/O link.
BACKGROUND OF THE INVENTION
One limitation on the throughput of a computer or other processing system is the interface between integrated circuits and/or other components in the system. Interface circuits often provide input/output (I/O) links for data transfers between components. Improved data transfer circuitry may allow faster and more efficient signaling between various components.
I/O links between components and systems often use data, reference voltage and strobe lines. The reference voltage provides a threshold which allows a signal to be qualified as low or high state, whereas the strobe provides the timing reference i.e. the position of the data bit in a time sequence. The strobe signal functions as a transfer clock. In some data transfer communications, glitches can occur in these signals. A glitch is generally defined as an undesired transition or bounce in a signal. Glitches destroy the integrity of signals on a line. Sources of glitches can include interference, cross talk, ground bounce, mechanical vibrations, etc. Data glitches can cause corruption of data if the glitch occurs at the sampling time at the receiver. Data error checking techniques such as parity or error-correcting code (ECC) can detect and possibly correct an error. However, any glitches in the strobe signal can alter the state machine and disturb the timing context, therefore corrupting future data. Therefore, a strobe glitch can have a catastrophic effect on the I/O link.
There are two types of strobe failures of concern. The first type is an analog glitch or noise that is long enough to cause errant internal strobe behavior, but does not manifest as a double pulse. This type of behavior can be difficult to detect. This error can amount to a slower signal transition edge or a moved edge, but not a full transition. During such a failure, the phase of the strobe with respect to the incoming data could be lost. The second type of strobe failure involves signal noise that creates a double pulse that may be mistakenly counted at the receiver. A double pulse can cause the logic in a state machine to erroneously increment to the next state.
One existing glitch protection scheme can only protect against glitches during master changeover scenarios. Another existing scheme can only detect an error and then flag the error during a break in bus activity. Other glitch protection schemes have uses a phase locked loop (PLL) to filter strobe signals. However, a PLL also filters out data and strobe cycle to cycle timing jitters, leading to undesired loss of timing margin.
FIG. 1
illustrates a block diagram of a typical prior art source synchronous strobe and data circuit
100
at a receiver. The circuit
100
receives a data signal
102
and a strobe signal
103
that have been sent from an external data transfer source. Data
102
is connected to a latch mechanism. The latch mechanism in this example is a set of first in/first out (FIFO) latches
118
. Strobe
103
is connected to a delayed lock loop (DLL)
112
. The DLL
112
is a chain of delay element that delays the propagation of strobe
103
to node
108
by a desired amount (usually 90°). The delayed version of strobe at node
108
is coupled to a write state machine (WSM)
120
at pointer
122
and latch enable logic
126
,
128
. Pointer
122
generates a plurality of latch select signals
124
based on transitions on strobe
103
. Latch enables
114
,
116
to the FIFO
118
are generated from latch enable logic
126
,
128
. For this example, latch selects
124
are logically anded together with delayed strobe
108
at and gates
126
,
128
.
The DLL
112
rotates STROBE
103
to a 90° position. This 90° phase shift allows the strobe signal to center the data window. However, the DLL
112
only performs a rotation and delays STROBE
103
. If STROBE
103
is noisy or has glitches, the noise and glitches are simply rotated 90° and propagated out to the WSM
120
.
This example circuit at the receiver end of the data transfer uses a strobe having a 90° rotation to advance the write pointer and latch incoming data. In other circuits, the strobe can be set at a 90° position at the driver end. But in either case, the noise and degraded signal quality can cause strobe glitches. It may be especially advantageous to identify options for strobe glitch protection and detection.
REFERENCES:
patent: 5519342 (1996-05-01), McEwan
patent: 5828257 (1998-10-01), Masleid
patent: 5872959 (1999-02-01), Nguyen et al.
Dabral Sanjay
Ilkbahar Alper
Du Thuan
Intel Corporation
Lam Peter
Lee Thomas
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