System for programmable chip initialization

Details System for programmable chip initialization System for programmable chip initialization

2000-12-12

2001-09-18

Zarabian, A. (Department: 2816)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S185250

Reexamination Certificate

active

06292409

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to the field of initialization of control systems, and more particularly to a system for programmable chip initialization wherein the Reset state of the controller such a system is initialized.
BACKGROUND OF THE INVENTION
Multiple levels of initialization are required for various control systems. The lowest or first level of initialization is signaled to begin with the assertion and de-assertion of the system “Reset” signal. When Reset is asserted the Controller device (see
FIG. 1
) is put into a known state and when Reset is de-asserted the Controller begins a sequence of operations which is dictated by the Controller's initial (i.e., Reset) state. Subsequently, the Controller may begin the next level of system initialization. This level might be to begin execution of commands fetched from EPROM (Erasable Programable Read Only Memory) or some other type of non-volatile memory, and/or to download initialization values from the same memory into it's local register set. Higher levels of initialization would follow and would be determined by software.
The present invention pertains to the lowest level of initialization where the Reset state of the Controller is determined. The current method of altering the Reset state of the Controller is shown in FIG.
1
. Shown is a simplified system
100
with a Controller device
102
and an EPROM device
104
interconnected with control, address, and data lines and sharing a common Reset input signal. While Reset is asserted the “Data0”, “Data1”, “Data2”, and “Data3” lines, are pulled to a resistive state as determined by the resistors “R0”, “R1”, “R2”, and “R3”, as the internal drivers in the EPROM and Controller devices
102
&
104
are turned off (i.e., placed in a high impedance state). Thus the Reset state is determined by the resistors which are connected to either a high level (VDD) or a low level (VSS). When Reset is de-asserted the values on the “Data0”, “Data1”, “Data2”, and “Data3” lines are captured by the Controller
102
as the Reset state of those lines and the following state sequences of the Controller
102
will be conditional on the initial state of those lines. This allows the Controller
102
, for example, to vary it's starting address in program memory from which to fetch commands. As shown in the timing diagram
200
of
FIG. 2
, at time “t1”
202
, the Reset signal is asserted and the Data Bus (signals “Data0”, “Data1”, “Data2”, and “Data3” of
FIG. 1
) transitions to the resistive pull values at time “t2”
204
. At time “t3”
206
, Reset is de-asserted and the Pull Value of the Data Bus is captured internally to the Controller
102
(
FIG. 1
) as the Initialization Value at time “t4”
208
.
Presently, the initialization configuration of control systems such as system
100
is physically selected by soldering pull-up (or pull down) resistors (e.g., resistors “R0”, “R1”, “R2”, and “R3”) to the system's circuit board. Further, the pull values for the data lines are set with mechanical switches or jumpers which would also be located on the circuit board that would select between the VSS (low) or VDD (high) supplies for each of the data lines. To change the pull values in the system the user would have to remove the board from the system and physically change the switch or jumper settings according to their specific needs. Thus, changing of chip (SCSI Controller) initialization options would require hardware changes to the system circuit board. Such changes are costly and difficult to implement. Consequently, it is desirable to provide a method and apparatus for programmable chip initialization wherein the Reset state of the controller of such a system is initialized.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a programmable input/output (I/O) pad internal resistive pull circuit assembly for a non-volatile memory device of a control system capable of providing programmable chip (SCSI Controller) initialization. In an exemplary embodiment, the assembly includes a non-volatile memory cell disposed in the non-volatile memory device. First and second transistor devices are coupled to the non-volatile memory cell. The non-volatile memory cell is capable of being programmed for providing at least one of a pull-up and a pull-down on an associated signal line of the non-volatile memory device thereby furnishing a predetermined reset value to a controller device of the control system.
It is to be understood that both the forgoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.


REFERENCES:
patent: 5455923 (1995-10-01), Kaplinsky
patent: 6078541 (2000-06-01), Kitagawa

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