System for preventing power save mode during a pre-set...

Electrical computers and digital processing systems: support – Computer power control

Reexamination Certificate

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Details

C713S320000, C713S321000, C713S323000

Reexamination Certificate

active

06594767

ABSTRACT:

FIELD OF THE INVENTION
This invention relates in general to computing technology and, more particularly, to a computer peripheral device prevented from being in power save mode.
BACKGROUND OF THE INVENTION
In order to minimize power usage during idle periods, modern printers and other computer peripheral devices include a power saving features often referred to as a sleep mode or power save mode. This feature is implemented by a manager with a timer in the device that puts the device into sleep mode after a pre-set idle period.
Many of the devices with the energy saving feature have a very long warm-up period. As a result, the first use of the device after the device has been in sleep mode takes much longer than a use of the device when it has not been in sleep mode.
Additionally, several printers with the energy saving feature perform calibration after exiting sleep mode. This calibration not only takes time to perform, but it also causes wear on the drum and other printing components. If a printer enters and exits the sleep mode several times a day, the life of many of the components of the printer can be reduced by several times over what could be achieved if the printer were to stay out of sleep mode.
SUMMARY OF THE INVENTION
According to principles of the present invention, a computer peripheral device is prevented from being in power save mode. A timing mechanism tracks time. The time is compared to a pre-set condition stored in a storage device. If the time meets the pre-set condition, the computer peripheral device is prevented from being in power save mode.
According to further principles of the present invention, the timing mechanism either tracks the time of day, the day of the week, an elapsed time, or a combination of these times.
According to further principles of the present invention, the computer peripheral device is prevented from being in power save mode by either forcing the peripheral device out of power save mode or preventing the peripheral device from entering power save mode. The computer peripheral device is forced out of power save mode by either transmitting a job to the peripheral device for processing or accessing the control means of the peripheral device and terminating the power save mode. The peripheral device is prevented from entering power save mode by periodically transmitting a job to the peripheral device for processing or temporarily disabling the power save mode for the peripheral device.
Other objects, advantages, and capabilities of the present invention will become more apparent as the description proceeds.


REFERENCES:
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patent: 5657257 (1997-08-01), Lee
patent: 5900026 (1999-05-01), Ryu
patent: 5978923 (1999-11-01), Kou
patent: 6044473 (2000-03-01), Kim
patent: 6384853 (2002-05-01), Shaffer et al.
patent: 6408395 (2002-06-01), Sugahara et al.
patent: 0735457 (1996-03-01), None
patent: 2265232 (1993-02-01), None
patent: 2290637 (1994-06-01), None
UK Patent Office Search Report.

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