Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-01-08
2004-08-03
Chen, Kin-Chan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S745000
Reexamination Certificate
active
06770565
ABSTRACT:
BACKGROUND OF THE DISCLOSURE
1. Field of the Invention
The present invention relates to planarizing metal conductive layers, more particularly to planarizing metal conductive layers for use in integrated circuits and other electronic devices.
2. Description of the Background Art
Integrated circuits have evolved into complex devices that can include millions of components (e.g., transistors, capacitors, and resistors) on a single chip. The evolution of chip designs continually requires faster circuitry and greater circuit density. The demands for greater circuit density necessitate a reduction in the dimensions of the integrated circuit components.
Sub-quarter micron, multi-level metallization is one of the key technologies for the next generation of ultra large scale integration (ULSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, lines and other features. Reliable formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die.
As circuit densities increase, the widths of vias, contacts, lines, plugs and other features, as well as the dielectric materials between them, decrease to less than 250 nanometers. The thickness of the dielectric layers, however, remains substantially constant, with the result that the aspect ratios for the features, i.e., their height divided by width, increases. Due to copper's electrical performance at such small feature sizes, copper has become a preferred metal for filling sub-quarter micron, high aspect ratio interconnect features on substrates.
In order to fill high aspect ratio features copper is typically electroplated to a thickness that exceeds the height of the feature, resulting in the deposition of copper in the “field” region above the feature. The copper is then typically planarized using a chemical mechanical planarization (CMP) process in order to remove copper from the field and to provide a smooth surface. Subsequent to CMP, dielectric and other material layers are deposited atop the metal feature.
However, CMP processes used to planarize metal conductive layers, particularly copper layers, use chemical slurries of abrasive materials which are aggressive and can damage dielectric material layers adjacent to the metal conductive layer. Furthermore, metals such as copper show tendencies to form various defects during CMP processing.
Furthermore, the system for deposition and planarization of copper that is commonly used in integrated circuit manufacture requires depositing the metal conductive layer in an electroplating metal deposition platform, planarizing the metal conductive layer using a CMP platform, and then depositing a dielectric layer using a third platform. The use of three separate platforms reduces overall system throughput and provides increased opportunities for contamination of the wafer and devices thereon.
Therefore, a need exists for a system for planarizing metal conductive layers that is less aggressive than CMP and is compatible with integrated circuit processing.
SUMMARY OF THE INVENTION
The present invention generally provides a method of planarizing a metal conductive layer on a substrate. In one embodiment, a substrate having a metal conductive layer disposed on a top surface of the substrate is provided on a substrate support. The substrate support is rotated and the top surface of the substrate is contacted with a liquid etching composition in order to remove portions of a top surface of the metal conductive layer. The metal conductive layer is then exposed to an etchant gas in order to planarize the top surface of the metal conductive layer.
In another embodiment, a substrate having a metal conductive layer disposed on a top surface of the substrate is provided on a substrate support. The substrate has stray metal conductive material on one or more other surfaces, such as an edge or bottom surface of the substrate. The substrate support is rotated and the top surface of the substrate is contacted with a liquid etching composition in order to remove portions of a top surface of the metal conductive layer. One or more other surfaces of the substrate are contacted with a second liquid etching composition in order to remove stray metal conductive material. The metal conductive layer is exposed to an etchant gas in order to planarize the top surface of the metal conductive layer.
In another embodiment, a metal conductive feature is formed on a substrate. A substrate having a metal conductive layer disposed on a top surface of the substrate is provided on a substrate support. A material layer is provided on the top surface of the substrate, and the material layer has at least one opening therethrough. A metal conductive layer is deposited on the substrate such that the metal conductive layer completely fills the opening. The substrate is rotated and the top surface of the substrate is contacted with a liquid etching composition in order to remove portions of a top surface of the metal conductive layer. The metal conductive layer is then exposed to an etchant gas in order to planarize the top surface of the metal conductive layer.
Also provided is an apparatus for etching a metal conductive layer on a substrate. The apparatus comprises a container, a substrate support disposed in the container, a rotation actuator attached to the substrate support, and a fluid delivery assembly disposed in the container to deliver liquid etching composition to a top surface of a substrate disposed on the substrate support.
The present invention provides an efficient method for planarizing metal conductive layers without the problems that accompany the use of abrasive polishing processes. By using the method of the present invention one may reduce the number of process platforms and improve process throughput.
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pate
Lubomirsky Dmitry
Olgado Donald J. K.
Tepman Avi
Webb Timothy R.
Applied Materials Inc.
Chen Kin-Chan
Moser Patterson & Sheridan
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