System for performing high speed burst operation in memory devic

Electrical computers and digital data processing systems: input/ – Input/output data processing – Data transfer specifying

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Details

711105, 711111, 711167, 713401, 713501, 713600, G06F 104, G06F 112

Patent

active

060062908

ABSTRACT:
Disclosed a conrol method and an apparatus for performing high speed burst operation in memory device which can perform high speed burst read/write operations at a speed superior to be superior to an operation speed of a burst EDO mode type DRAM by shortening a CAS access time tCAC, and can produce an identical package using signals which are used in a memory device of a EDO mode type DRAM. The method comprising the steps of preparing an "Idle" status where an internal circuit is precharged after a "Power On" status, determining a read mode, a write mode, a read/write mode, or a write/read mode in accordance with a /WE signal at a falling edge of a /CAS signal in which a column address is inputted in a case of a "Row Open" status by an instruction which is inputted during the "Idle" status, and automatically returning to the "Row Open" status if an operation of the read, write, read/write, or write/read mode is ended. Accordingly, the present invention can be used for a 66 MHz bus clock frequency which can not be applied to the conventional burst EDO mode type DRAM, and for the next generation 75-100 MHz bus clocks frequency. Further, there is an advantage that the present invention does not use the external clock, unlike a synchronous type DRAM, thereby reducing the power consumption of the total memory system.

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patent: 5857095 (1999-01-01), Jeddeloh et al.

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