Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2007-08-31
2011-12-20
Tabone, Jr., John J (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S764000, C714S768000, C714S718000, C714SE11034, C714S006240, C365S201000
Reexamination Certificate
active
08082482
ABSTRACT:
A memory system is provided for performing error correction operations in a memory module. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub device comprises a link interface integrated into the memory hub device that provides a communication pathway between an external memory controller and the set of memory devices. The memory hub device also comprises first error correction logic provided in write logic integrated in the memory hub device, the write logic providing a data path for writing data to the set of memory devices. The memory hub device also comprises second error correction logic provided in read logic integrated in the memory hub device, the read logic providing a data path for reading data from the set of memory devices.
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Notice of Allowance mailed Dec. 3, 2010 for U.S. Appl. No. 12/018,972; 5 pages.
Notice
Gower Kevin C.
Maule Warren E.
Gerhardt Diana R.
International Business Machines - Corporation
Lammes Francis
Tabone, Jr. John J
Walder, Jr. Stephen J.
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