System for performing cache flush transactions from interconnect

Details System for performing cache flush transactions from interconnect System for performing cache flush transactions from interconnect

1997-12-17

1998-10-27

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711143, 711144, 711121, G06F 1212

Patent

active

058290303

ABSTRACT:
A fault tolerant computer which executes the cache flush operation at a high speed and has the real time characteristic. A processor module 301 is equipped with a cache memory so that the entry address of the updated cache block within the cache memory is stored in a stack. The cache flush is effected only with respect to the entry address in the stack when a recovery-point setting condition due to a timer or the like is satisfied. A memory module 303 has an arrangement doubled in the same storage physical space and is equipped with a buffer memory for temporarily storing the transferred cache block, so that the cache block is simultaneously transferred to a pair of buffer memories.

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