Electrical computers and digital processing systems: processing – Processing control – Branching
Patent
1998-11-12
2000-06-27
An, Meng-Ai T.
Electrical computers and digital processing systems: processing
Processing control
Branching
G06F 932
Patent
active
060818875
ABSTRACT:
A technique for predicting the result of a conditional branch instruction for use with a processor having instruction pipeline. A stored predictor is connected to the front end of the pipeline and is trained from a truth based predictor connected to the back end of the pipeline. The stored predictor is accessible in one instruction cycle, and therefore provides minimum predictor latency. Update latency is minimized by storing multiple predictions in the front end stored predictor which are indexed by an index counter. The multiple predictions, as provided by the back end, are indexed by the index counter to select a particular one as current prediction on a given instruction pipeline cycle. The front end stored predictor also passes along to the back end predictor, such as through the instruction pipeline, a position value used to generate the predictions. This further structure accommodates ghost branch instructions that turn out to be flushed out of the pipeline when it must be backed up. As a result, the front end always provides an accurate prediction with minimum update latency.
REFERENCES:
patent: 5564118 (1996-10-01), Steely, Jr. et al.
patent: 5752014 (1998-05-01), Mallick et al.
patent: 5903751 (1999-05-01), Hoyt et al.
patent: 8646975 (1999-01-01), Shiell
Emer et al. (A language for describing predictors and its application to automatic synthesis) Internation Symposium on computer architecture 1-11, Jun. 1997.
Yeh, T., et al., "Two-Level Adaptive Training Branch Prediction," (1991).
Keller, J. et al., "A Superscaler Alpha Processor with Out-of-Order Execution," Microprocessor Forum, (Oct. 1996).
Gieseke, B.A., et al., "A 600MHz Superscalar RISC Microprocessor With Out-of-Order Execution," (undated).
Gwennap, L., "Digital 21264 Sets New Standard--Clock Speed, Complexity, Performance Surpass Records, But Still a Year Away," Microprocessor Report, 10(14) :1-11, (Oct. 28, 1996).
Gieseke, B.A., et al., "A 600MHz Superscaler RISC Microprocessor With Out-of-Order Execution," IEEE International Solid-State Circuits Conference, (1997).
Emer Joel S.
McLellan Edward J.
Steely, Jr. Simon C.
An Meng-Ai T.
Compaq Computer Corporation
Patel Gautam R.
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