System for optimizing the testing and repair time of a defective

Details System for optimizing the testing and repair time of a defective System for optimizing the testing and repair time of a defective

1998-09-09

2000-10-03

Nguyen, Hoa T.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

714719, G11C 2900

Patent

active

061287563

ABSTRACT:
A method and apparatus for testing semiconductor memory chips, such as DRAMs, having a plurality of memory cells or bits. Each memory chip has a unique identifier stored in a database. Tests are performed on the memory chips and when a memory chip fails a test, the memory chip is placed in a repair bin and a test identifier is stored in the database in association with the memory chip identifier. In order to repair the memory chip, failed tests are read out of the database and such tests are again performed on the failed memory chip in order to determine which memory cell in the memory chip is faulty. The failed memory cells are then repaired.

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patent: 4510673 (1985-04-01), Shils et al.
patent: 5465850 (1995-11-01), Kase
patent: 5550838 (1996-08-01), Okajima
patent: 5867505 (1999-02-01), Beffa

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