Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2000-01-06
2003-01-28
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S501000, C713S502000, C713S503000, C713S600000
Reexamination Certificate
active
06513126
ABSTRACT:
BACKGROUND
When implementing a hardware design, it is often desirable to be able to model the behavior of the hardware design during the design process. Modeling of the behavior of the design allows the designer to quickly simulate and determine the performance of the design before completion and to make any necessary changes. Such a model is often utilized when a design includes interfacing two or more devices. For example, in an audio processing system, a digital signal processor (DSP) may be used to implement one or more audio processing algorithms. The output of the digital signal processor may then be passed through an interface to an encoding device that encodes the output into a format that is suitable for transmitting the DSP output to an intended receiving device. Often, the clock rate of the DSP and the clock rate of the encoding device are different such that it is desirable to determine and control the behavior of one device with respect the other. In some instances, it is desirable to account for multiple clocks. It would be advantageous for a designer to be able to model the interface behavior for at least one or more clock rates of at least one or more clocks. Furthermore, running a simulation on a general purpose simulator requires a simulation model that is too large and too slow to run a cycle-by-cycle simulation, especially in an asynchronous domain for asynchronous hardware. Thus, there lies a need for a system and apparatus by which the design of an interface may be modeled.
REFERENCES:
patent: 4258300 (1981-03-01), Fromont
patent: 5570455 (1996-10-01), Remillard
patent: 5758133 (1998-05-01), Evoy
patent: 5796995 (1998-08-01), Nasserbakht et al.
Huang Wen
Wu Scarlett
Lee Thomas
LSI Logic Corporation
Suiter & Associates PC
Yanchus, III Paul
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