Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Counting – scheduling – or event timing
Reexamination Certificate
2000-04-11
2003-06-24
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Counting, scheduling, or event timing
C713S600000, C710S058000, C711S167000, C714S719000, C714S824000, C365S201000
Reexamination Certificate
active
06584577
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a device for measuring the response time of a circuit and to a method of measuring the response time of a circuit.
More particularly, but not exclusively the invention relates to a method of determining the response time of a deeply embedded memory, for example a static RAM and to a device for determining the response time of a deeply embedded memory, for example a static RAM.
BACKGROUND OF THE INVENTION
Current techniques for evaluating embedded fast SRAM designs use either extremely high performance testing devices, which are costly or alternatively require physical access to internal nodes. The latter tends to be inaccurate and is not capable of providing statistical sampling over long periods of time.
It will be desirable to provide a method and device capable of providing statistical data on a number of circuits and to use conventional test apparatus to collect statistically significant data.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention there is provided a device for measuring the response time of a circuit, the circuit having an output for providing a response to a stimulus at an input node thereof, the device comprising first circuitry having a clock node and an output, said first circuitry being connected to store an output condition, said output condition corresponding to a state of said circuit output at the time of occurrence of a clock pulse at said clock node, the device further comprising second circuitry and third circuitry, said second circuitry being responsive to a second circuitry input signal at its input to provide said stimulus at said input node of said circuit, and said third circuitry being responsive to a third circuitry input signal at its input to provide a clock pulse at said clock node whereby said response time is determined by the time between said second circuitry input signal and said third circuitry input signal, wherein said second circuitry has an output connected to said input node, and said third circuitry has an output connected to said clock node, and a delay between the input to said second circuitry and its output is substantially the same as a delay between the input and output of the third circuitry.
Preferably, said circuit comprises a memory, having address latch circuitry with a clock input as said circuit input node, an array of memory cells coupled to said address latch circuitry and sense amplifier circuitry connected to said array, said sense amplifier circuitry having a sense amplifier output as said circuit output.
Advantageously said memory is an embedded memory.
Advantageously said embedded memory comprises a SRAM.
Advantageously the first circuitry comprises flip-flop circuitry.
According to a second aspect of the present invention there is provided a device for measuring a response time of a circuit between an input node and a circuit output thereof, wherein said circuit output is connected via first connecting circuitry to an output pad, said device comprising a first timing signal source for providing a first timing signal to said input node via a first path having a first delay, clocked circuitry having a clock node and being connected at said circuit output, said clocked circuitry having an output to said first connecting circuitry, said clocked circuitry being responsive to a clock signal at said clock node to provide to said first connecting circuitry a signal existing at said circuit output immediately prior to the occurrence of said clock signal, the device further comprising a second timing signal source for providing a second timing signal as said clock signal to said clock node via a second path having a second delay substantially equal to said first delay, and means for determining a time period between said first and second timing signals.
Advantageously said clocked circuitry comprises a flip-flop.
Preferably the device further comprises a sensing device connected to said output pad for sensing a desired output thereat.
Preferably again said circuit comprises a static RAM.
Conveniently said static RAM comprises address latch circuitry having a latch clock node as said input node, an array of memory cells coupled to said address latch circuitry, and sense amplifier circuitry having a sense amplifier output node as said output node.
According to a further aspect of the present invention there is provided a method of measuring the response time of a circuit having a circuit output for providing an output in response to a stimulus applied to a circuit input, the circuit input being connected to a first input pad via first circuitry having a predetermined delay, the method comprising:
providing second circuitry having a clock node, said clock node being connected to a second input pad via third circuitry, said third circuitry having said predetermined delay, and said second circuitry having an output for storing an output condition, said output condition corresponding to the state of said circuit output at the time of occurrence of a clock pulse at said clock node;
repeatedly applying a stimulus to said first input pad and at a variable delay after each application, providing a clock pulse to said second input pad; and
determining, as said response time, a value of said variable delay corresponding to a desired output condition of said second circuitry.
Preferably said second circuitry is coupled to an output pad, and said determining step comprises monitoring said output pad.
Advantageously said desired output condition is a valid condition such that reduction of said variable delay produces an invalid condition.
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European Standard Search Report from GB 0010942, filed May 11, 1999.
Du Thuan
Lee Thomas
STMicroelectronics Limited
Wolf Greenfield & Sacks P.C.
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