Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2000-04-13
2003-10-21
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C714S798000, C714S799000, C375S215000, C342S103000
Reexamination Certificate
active
06636979
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor integrated circuits and, more particularly, to a circuit for measuring phase error between two clock signals on the integrated circuit.
Clock signals are used in semiconductor integrated circuits for clocking sequential elements of the circuit. A typical integrated circuit uses multiple individual clock signals having the same or different frequencies for operating various portions of the integrated circuit. In order to minimize timing errors between sequential elements, it is desirable to minimize the phase error between individual clock signals. The phase error between two clocks on an integrated circuit can vary from one integrated circuit to the next due to variances in process, voltage and temperature, known as “PVT”. The variations in process can be caused by fabrication tolerances of the individual semiconductor devices and their interconnects on the integrated circuit. Phase errors exceeding a specified timing margin can induce errors in functionality and other performance problems on the integrated circuit.
For example, phase error between two clocks is an important factor in the operation of phase-locked loops (PLLs). PLLs are used in integrated circuits, such as application specific integrated circuits (ASICs) for clock synchronization and for recovery of serial data streams. Once a PLL has locked a reference feedback signal onto the phase and frequency of an input signal, any remaining phase error between the reference feedback signal and the input signal is known as “jitter”. Depending on PLL performance and implementation, the PLL jitter can become unacceptably large for a particular integrated circuit. This can lead to difficulties in clock synchronization or accurate recovery of serial data streams.
SUMMARY OF THE INVENTION
One aspect of the present invention is directed to a phase error measurement circuit for estimating phase error between two clock signals on an integrated circuit. The measurement circuit includes first and second clock signal inputs, a phase lead detector, a phase lag detector and a phase error measurement output. The phase lead detector includes a phase lead latch having a data input, which is coupled to the first clock signal input, a latch control input, which is coupled to the second clock signal input and a data output. The phase lag detector includes a phase lag latch having a data input, which is coupled to the second clock signal input, a latch control input, which is coupled to the first clock signal input and a data output. The phase error measurement output is formed by the data outputs of the phase lead latch and the phase lag latch.
Another aspect of the present invention is directed to a phase error measurement circuit, which includes a first clock signal input and a second clock signal input. A delay circuit delays the first clock signal input by a phase lead measuring delay to produce a delayed first clock signal input. A further delay circuit delays the second clock signal input by a phase lag measuring delay to produce a delayed second clock signal input. A phase lead measuring circuit detects whether the delayed first clock signal input leads the second clock signal input, and a phase lag measuring circuit detects whether the delayed second clock signal input leads the first clock signal input.
Another aspect of the present invention is directed to a method of measuring phase error between first and second clock signals on an integrated circuit. The method includes: delaying the first clock signal by a phase lead delay to produce a delayed first clock signal; latching the delayed first clock signal with an edge-triggered phase lead latch as a function of the second clock signal to produce a phase lead indicating output signal; delaying the second clock signal by a phase lag delay to produce a delayed second clock signal; latching the delayed second clock signal with an edge-triggered phase lag latch as a function of the first clock signal to produce a phase lag indicating output signal; and generating signal indicative of the phase error between the first and second clock signals relative to the phase lead delay and the phase lag delay based on the phase lead indicating output and the phase lag indicating output.
Yet another aspect of the present invention is directed to a phase-locked loop, which includes a phase detector, a charge pump, a loop filter, a voltage-controlled oscillator and a phase lock detector. The phase detector has a clock input, a feedback input, and a charge control output. The charge pump is coupled to the charge control output, and the loop filter is coupled to the charge pump. The voltage controlled oscillator has a control voltage input coupled to the loop filter and a clock output coupled to the feedback input. The phase lock detector includes a phase lead detector, a phase lag detector and a phase lock signal generator. The phase lead detector includes a phase lead latch having a data input coupled to the feedback input, a latch control input coupled to the clock input, a data output and a phase lead delay from the feedback input to the data output. The phase lead delay represents a threshold phase difference between the feedback input and the clock input under which the phase-locked loop is in a lock state. The phase lag detector includes a phase lag latch having a data input coupled to the clock input, a latch control input coupled to the feedback input, a data output and a phase lag delay from the clock input to the data output, which represents the threshold phase difference. The phase lock signal generator receives the data outputs of the phase lead and phase lag latches and responsively generates a phase lock signal indicative of whether the phase-locked loop is in the lock state.
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Christiansen Joel J.
Flanagan Ian MacPherson
Reddy Dayanand K.
Lee Thomas
LSI Logic Corporation
Nieves Michael
Westman, Champlin & Kelly, P.C.
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