Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output addressing
Reexamination Certificate
1998-06-12
2001-01-23
Lee, Thomas C. (Department: 2782)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output addressing
C710S107000, C710S120000, C709S207000
Reexamination Certificate
active
06178466
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to an interface and interface control system for transferring signals between various units in a data processing system; and, more specifically, relates to an improved interface and interface control system for transferring address and data signals via independently and asynchronously operative address and data interfaces, respectively.
2. Discussion of the Prior Art
Data processing systems generally include multiple units such as processing units, memory units, input/output units, and the like, which are interconnected over one or more system interfaces. The interfaces provide for the transfer of digital signals between the units. Since many of the operations within data processing systems involve such transfers, the efficiency of the interfaces has a major impact on the overall performance of the data processing system.
Many conventional interfaces used within data processing systems have several types of signal lines, including data lines for transferring data signals, and address lines for transferring address signals. The address lines generally provide information indicative of the type of request, and further indicate a unit and/or a particular addressable resource associated within the unit that is involved with the request. The data lines provide data signals which are associated with the request.
In many data processing systems, the address and data lines operate in a lock step fashion. That is, for a given request utilizing a system interface, the address signals and data signals are transferred over the interface during operations which have a predetermined relationship to one another. The requesting unit will retain control of both the address and data lines during the entire transfer, even if the address lines, data lines, or both, are idle during a portion of that transfer. For example, often, the address lines are needed only during the time required for the addressed unit to receive and decode the request. If data signals are associated with the request, the address lines will remain idle during the time required to perform the data transfer. Because the requesting unit retains control over the unused address lines, no other unit in the system may use the address interface to initiate a request, thereby diminishing overall performance. Similarly, some requests may only involve the address lines. Forcing the data lines to remain idle during this time also limits system throughput.
To increase system throughput, some systems provide data and address interfaces which do not operate in lock step fashion. In these types of systems, a unit may relinquish control of the address lines while still maintaining control of the data lines. This allows a different unit to initiate a request over the address lines while a first request completes over the data lines so that a higher throughput rate is achieved. Although allowing data and address transfers to occur in other than a lock step manner increases system throughput, some method is needed to correlate data and address signals associated with the same request. One method is to utilize identification information to associate data signals with later transferred address signals or vice versa. A system using this approach is disclosed in U.S. Pat. No. 5,237,567 to Nay et al. This system includes an identification bus having lines dedicated to transferring information identifying the requester, receiver, and the source of the data. This information is included with both address and data transfer operations so that separate data and address transfers may be correlated as being associated with the same request. The Nay system further attempts to simplify the correlation process by requiring that during any write operation, a requester must provide the data signals in the same bus cycle as the address signals. Thus, in Nay, data and address interface independence is only truly achieved for read operations, but not for write operations, limiting interface flexibility. Additionally, the Nay system requires additional interface lines to perform the correlation between data and address components of a request. In units having a limited number of interface resources such as pins, this solution is undesirable.
A system using an approach similar to that described by Nay is disclosed by U.S. Pat. No. 5,235,685 to Caldara et al. Caldara describes an I/O interface having independent command and data lines. The command lines are used to initiate an I/O transfer to or from ones of the I/O units connected to a master, and data lines are used to provide associated data signals during a later independent data transfer operation. The command and data transfers are correlated using a dedicated ten-line control interface. This system, like the Nay system, has the disadvantage of requiring an additional dedicated interface to associate data signals with earlier-provided command signals. Moreover, the Caldara system requires that for any given transfer operation, the command signals must be transferred prior to the associated data signals. This reduces interface flexibility.
Another system for correlating operations occurring on quasi-independent data and address interfaces is disclosed in U.S. Pat. No. 5,666,551 to Fenwick et al. In the Fenwick system, each unit interfacing to the data bus includes a data sequencer which keeps a running count of the number of outstanding transfers on the address bus which are awaiting an associated data transfer. The sequencer also records which of those outstanding transfers will involve the unit with which that sequencer is associated. The priority logic orders transfers on the data bus by selecting the unit associated with the next sequence number. The Fenwick method has the disadvantage of requiring all units to respond in sequence order. For example, two outstanding read operations must be completed in the order the addresses were provided to the memory units, even if the later-initiated operation involves a faster memory device capable of providing data prior to the first memory device. This sequenced approach therefore does not result in optimal throughput. Moreover, since every unit transferring data must include a logic sequencer, the solution is relatively logic intensive.
What is needed is a system for allowing data and address transfers to occur in a truly independent fashion without requiring additional interface lines to correlate data and address transfers. To provide for optimal throughput, the independent data and address lines should be capable of providing data signals prior to associated address signals and vice versa. Moreover, the order of processing requests should not be predicated on the order in which address signals are transferred.
Objects
The primary object of the invention is to provide an improved control system for a data processing system having independent address and data interfaces;
A further object of the invention is to provide independent address and data interfaces for a data processing system wherein a predetermined maximum number of address requests may be transferred via the address interface before any associated data signals are transferred via the data interface;
A yet further object of the invention is to provide independent address and data interfaces for a data processing system whereby data signals may be provided via the data interface prior to associated address signals being provided via the address interface;
A still further object of the invention is to provide independent address and data interfaces for a data processing system whereby address and data signals transferred during independent transfers are correlated without the use of dedicated interface signals;
Another object of the invention is to provide independent address and data interfaces for initiating requests and transferring respective data signals, respectively, and whereby the initiated requests need not be processed in the order in which they are initiated;
A further object of the invention is to provide a
Bauman Mitchell Anthony
Gilbertson Roger Lee
Atlass Michael B.
Elamin Abdelmoniem
Johnson Charles A.
Lee Thomas C.
McMahon Beth L.
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