System for managing write and/or read access priorities between

Details System for managing write and/or read access priorities between System for managing write and/or read access priorities between

1997-04-23

1998-07-28

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

364DIG1, 364DIG2, 3642461, 711150, 711154, 711168, G06F 1200, G06F 1300

Patent

active

057874816

ABSTRACT:
A system for managing write and/or read access priorities between a central processing unit (CPU) and at least one memory (11) which includes mechanism for managing invalid accesses to the memory, The system comprises: an address comparator (19) able to test at each time instant the equality of the write and read addresses in memory, and in the event of equality of the addresses, to generate a signal (35) representative of a condition of invalid access to the memory. A diversion multiplexer circuit (27) is controlled by the invalid access signal (35), in such a way as to connect the bus (33) for reading to the CPU, either to the memory data read bus (31;31') in the event of the absence of an invalid access, or to the bus (29;29') for writing data from the CPU to the memory in the event of invalid access signal being present, so that the memory data write bus is diverted to the read bus by the CPU in the event of an attempted invalid access of the memory by the CPU.

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