Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2005-01-18
2005-01-18
Ellis, Kevin L. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S133000, C707S793000
Reexamination Certificate
active
06845430
ABSTRACT:
In a multi-threaded computing environment, a shared cache system reduces the amount of redundant information stored in memory. A cache memory area provides both global readable data and private writable data to processing threads. A particular processing thread accesses data by first checking its private views of modified data and then its global views of read-only data. Uncached data is read into a cache buffer for global access. If write access is required by the processing thread, the data is copied into a new cache buffer, which is assigned to the processing thread's private view. The particular shared cache system supports generational views of data. The system is particularly useful in on-line analytical processing of multi-dimensional databases. In one embodiment, a dedicated collector reclaims cache memory blocks for the processing threads. By utilizing a dedicated collector thread, any processing penalty encountered during the reclamation process is absorbed by the dedicated collector. Thus the user session threads continue to operate normally, making the reclaiming of cache memory blocks by the dedicated collector task thread transparent to the user session threads. In an alternative embodiment, the process for reclaiming page buffers is distributed amongst user processes sharing the shared memory. Each of the user processes includes a user thread collector for reclaiming a page buffer as needed and multiple user processes can concurrently reclaim page buffers.
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Carey James E.
Golbus Bruce F.
Hopeman Albert A.
Ellis Kevin L.
Hamilton Brook Smith & Reynolds P.C.
Oracle International Corporation
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