System for logic extraction from a layout database

Details System for logic extraction from a layout database System for logic extraction from a layout database

1998-02-23

2000-12-26

Lintz, Paul R.

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

716 2, 716 7, G06F 1750

Patent

active

061675563

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to automated design of integrated circuits, and more particularly to the extraction of a logic design from a layout database or a transistor level net list of a logic block.
2. Description of Related Art
Integrated circuits often include complex logic blocks. The design and implementation of such logic blocks is a difficult and time consuming task. It is often desirable to use logic blocks which have been successfully implemented in old integrated circuits, in a new product. For example, a new product that might be more highly integrated including more functions on a single chip, or a new product made using more modem process technologies, may be desired in which a logic block implemented in an old integrated circuit could be directly applied.
However, logic blocks in old integrated circuits often only exist in a physical form. Thus, there is no description of the logic implemented by the logic block at a level of sufficient detail to allow it to be readily ported to a new product or a new process technology. There are existing products on the marketplace that are able to translate a polygon layout description of an integrated circuit into a transistor level net list. See for example, Design Rule Enforcement and Migration DREAM, provided by Sagantec Israel Ltd., of Haifa, Israel. However, the transistor level net list is still insufficient to provide source material for porting the logic block to new process technologies in many circumstances. Also, higher level description of the logic block is necessary to allow hardware emulation and critical path enhancement which might be necessary for successfully porting the old logic block to a new process technology, or to systems requiring different clock rates or other changing parameters of operation.
Accordingly, there is a need for a technique for extracting a logic gate level description of a logic block from a layout database or from a transistor level net list generated from a layout database. Such a technique would enable the recover of substantial intellectual property embodied by layout blocks in older integrated circuit designs. Furthermore, the technique will allow implementation of old designs with denser and faster processes, and with improved characteristics to fit new environments of use.


SUMMARY OF THE INVENTION

The present invention provides a system and process for logic extraction from the layout of logic blocks. Logic design information is extracted from a transistor level net list which is stored in a memory. The transistor level net list in turn is generated from a layout polygon database using techniques available in the art. The process comprises processing the transistor level net list in the memory to define groups of transistors according to a connection or not to a supply voltage, a connection or not to a reference voltage and the transistor type. The groups of transistors are analyzed according to their interconnections, and their membership in groups. Finally, logic units are identified in response to the step of analyzing the groups of transistors.
For example, the groups of transistors include a first group of transistors of a first type, such as p-channel MOS transistors, having a source node coupled to a supply voltage, such as a V.sub.DD supply voltage, a second group of transistors of the first type, such as the p-channel MOS transistors, having a source node that is not coupled to a supply voltage, a third group of transistors of a second type, such as a n-channel MOS transistor, having a source node not coupled to a reference voltage such as ground or a V.sub.SS supply voltage, and a fourth group of transistors of the second type having a source node coupled to a reference voltage. The groups are analyzed by determining for at least one of said groups of transistors, respective interconnected sets of transistors for particular transistors in said one group. The respective sets include the particular transistor, and transistors from the fi

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