Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2000-01-19
2003-06-10
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C345S547000, C345S558000, C365S189050
Reexamination Certificate
active
06578093
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates, generally, to the coupling of asynchronous electronic devices, and, in particular embodiments to synchronization of READ/WRITE pointers in a first in first out (“FIFO”) queue.
BACKGROUND OF THE INVENTION
The capability of electronic systems is increasing at a significant rate, as integrated circuit technology improves. The number of transistors which can be placed on an integrated circuit tends to double every 18 months according to a hypothesis which was accurately postulated by Gordon Moore of Intel Corp. over twenty years ago. As more transistors can be integrated into integrated circuits there is a proportional increase in processing power. Because of this increased processing power, applications having data manipulation intensive requirements, as speech recognition, Computer Aided Tomography (CAT) scanning, electronic games and real-time compression of television signals, are now possible.
In particular, the frequency of use and versatility of video data is increasing. For example, video data is used for electronic games, for video teleconferencing systems, for televisions, for Video Cassette Recorders (VCRs), to display movie images on computer monitors and for transmitting moving images via networks such as the internet. Moreover, different video components are often connected together. For example, a video encoder may be connected to a video decoder, and the video encoder and video decoder may transmit data to each other to encode or decode the data respectively.
The connected video components may have different clock rates. The clock rate is the speed at which a digital circuit operates. Every synchronous digital circuit contains one or more internal clocks that regulate the rate at which circuit operations are performed. These internal clocks synchronize the various circuit operations. Different synchronous digital circuits may have differing clock rates, or, even if they are the same clock rate, digital synchronous circuits may have clocks that drift with respect to each other. For example, the microprocessors contained in personal computers may have clock rates anywhere from 4 MHz to over 600 MHz. The faster the clock, the more instructions the microprocessor can execute per second. Clock speeds are generally expressed in megahertz, one megahertz being equal to one million cycles per second.
As data is transmitted from a first component to a second component, the second component may need to synchronize with the data that it is receiving from the first component. For example, a VCR which is recording a video signal on a tape must synchronize itself to the video signal that it is receiving from its tuner. Traditionally circuits containing phase lock loops are used to synchronize a video signal with a display. Another method for synchronizing data between components is by storing the data in a FIFO (First In First Out) queue. A FIFO queue is a data structure used by computing systems that is very similar in concept to the checkout line at a supermarket. Data, like the customers in a checkout line, arrive at the queue and then are taken in turn through the checkout.
In an application that utilizes a FIFO the data that is inserted in a FIFO first will be the first to come out of the queue, hence the designation First In First Out or FIFO. Data arrives in the FIFO and is stored for a period and then is removed, as the receiver of the data is able to accept it. In one scenario a video decoder writes data into a FIFO queue and the video encoder reads that data from the FIFO queue. Data may be written into the FIFO queue by a component with the first clock rate and then the data may be read out of the FIFO queue by a component with a second clock rate. The FIFO queue can be used for synchronization of data across different clock rate domains. The use of a FIFO queue to synchronize data between components of different clock rates has some inherent problems which must be dealt with if reliable operation is to be maintained.
One problem exists because of the different clock rates between the circuits. Because of the different clock rates, it is possible that more data can be written into the FIFO queue than it can hold, causing the FIFO queue to overflow. Overflow can also occur when the second component, which is removing data from the FIFO queue, does not remove data at a fast enough rate so that the data within the FIFO queue reaches a maximum limit. When an overflow condition occurs, some recovery mechanism must be instituted if the circuit is to resume normal operation.
Conversely, it is possible that the write operation will be slower than the read operation. When this condition is present, or if the writing stops into the FIFO queue, an underflow condition may occur. An underflow condition can occur when a circuit calls for data that has not yet been placed into the FIFO queue. In other words, the circuit may call for data that is not in the FIFO queue and hence old data from the queue may be re-read. When an underflow occur, some recovery mechanism must be instituted if the circuit is to resume normal operation. One method of avoiding overflow is to increase the size of the FIFO queue, thereby allowing it to contain more data before it overflows. A second method of attempting to maintain reliable operation between the two circuits is to adjust the clocks within the two circuits so that their frequencies are as close as possible. Neither of these methods are 100% effective. For example, increasing the size of a FIFO may be able to prolong the overflow of data within a FIFO, but it cannot stop the overflow from occurring. Also, in the case where the clocks of these two components have frequencies that are matched, there will still be some difference from the clock in the first component to the clock in the second component unless they are actually locked together. This timing gap will eventually cause an underflow or an overflow condition. In some systems, in addition to increasing the size of the FIFO queue and attempting to lock the clocking signals together, recovery circuits may be used. System designers accept the fact that completely preventing underflow or overflow is difficult and have developed methods to resynchronize the components which have become unsynchronized due to an underflow or overflow in the FIFO queue from which data will be read. In particular, the component that writes to the FIFO queue writes data to the address to which a write pointer points in the FIFO queue, and the component that reads data uses a read pointer, which specifies an address in the FIFO queue. For synchronization, the read and write pointers that point into the FIFO queue are realigned. Some systems perform this synchronization by using a reset control signal which sets both the read and the write pointer back to the address zero of the FIFO queue.
Additionally, some video systems reset a FIFO queue when in a vertical blanking interval (i.e., when no viewable data is being transmitted). Note that blanking refers to the part of a video transmission that has no viewable content, for example, to allow time when the television's electron gun is moving from the bottom to the top of the screen as it scans images. In many systems, this resetting of the read and write FIFO queue pointers occurs when it is known that no data should be in the queue, such as during a vertical blanking interval. When no data should be in the FIFO queue, both pointers may be reset to the same point, typically a zero address. A FIFO queue must be in a known state to reset both pointers and when the FIFO queue is in an empty state, both read and write pointers may be reset to the same point, indicating that the queue is empty. In some systems, the FIFO queue may not be expected to be empty except during vertical blanking, and read and write pointer synchronization cannot occur except during the vertical blanking period.
Conventional systems, however, do not provide aligning read and write pointers of a IFO queue at any time and at any sequential add
Armen Stephen F.
Felta Benjamin Edwin
Shakeel Asif
Conexant Systems Inc.
Foley & Lardner
Gaffin Jeffrey
Park Ilwoo
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