Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
1998-11-24
2001-08-07
Lee, Thomas (Department: 2782)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S002000, C711S105000, C711S119000
Reexamination Certificate
active
06272567
ABSTRACT:
The present invention relates to systems that switch and route data packets and cells amongst I/O source and destination resources through shared central memory cores comprised of multi-port internally cached dynamic random access memory chips, termed AMPIC DRAMs, of the type described in U.S. Pat. No. 5,799,209 issued Aug. 25, 1998 to Mukesh Chatter; being more particularly concerned with the control path section of such systems and problems with data traffic congestion created as the number of I/O resources in the system, and the system bandwidth requirements significantly increase, requiring a novel control path architecture that can scale with the datapath while retaining quality of services (QOS) and multicast features.
BACKGROUND OF INVENTION
The breakthrough afforded by the Chatter AMPIC DRAM architecture of data switching, and switching and routing amongst network I/O source and destination resources, as described in the above-referenced patent, has enabled orders of magnitude faster transfer of blocks of data internal to the chip, and the accommodation of significantly higher numbers of resources, with the reduction of current serious bandwidth limitations. This architecture has also given rise to higher performance, lower system latency, less data packet buffer memory requirements, better QOS features, and true multicast operation, which current and traditional networking architectures have been unable to achieve.
As the number of I/O resources in such systems explodes, and with it the concomitant demand for even further increases in bandwidth, however, the data packet information packet itself (herein termed “PIP”) becomes the limiting factor in this type of system, It is to the addressing of these issues through a novel control path architecture—itself adopting and using the AMPIC DATA technology also in the control path—that the present invention is concerned. The invention, indeed, creates a control path architecture for such AMPIC DATA switching and routing systems that scales with the data path, while still maintaining QOS functionality and providing improved multicast performance.
OBJECTS OF INVENTION
It is a primary object of the present invention, accordingly, to provide in systems for switching and routing data packets and/or cells amongst I/O source and destination resources through the shared memory AMPIC DRAM cores of said Chatter patent, a new and improved method of and system for obviating data packet congestion limitations with significantly increased I/O resources, that adopts and uses the AMPIC DRAM technology also within the control path architecture of the system, and that does so with features of scalability with the data path, while maintaining QOS and improved multicast features.
A further object is to provide a novel network control path architecture of more general utility, as well.
Other and further objects will be explained hereinafter and are more particularly delineated in the appended claims.
SUMMARY
In summary, however, from one of its important aspects, the invention embraces in a network for interfacing parallel I/O data packet information packets (PIP) source resources with I/O destination resources through a central shared memory datapath comprised of a central shared multi-port internally cached DRAM memory system (AMPIC DRAM) and a separate control path therefor, and wherein each I/O resource has the capability simultaneously to receive PIP data stream traffic from all other I/O resources, a method of eliminating PIP traffic congestion as the number of I/O resources and/or bandwidth requirements significantly increase, that comprises, interposing an AMPIC DRAM system in the control path for simultaneously absorbing and storing all PIP streams without stalling an I/O source resource incoming data stream.
Preferred and best mode designs, systems and operational methods therefor are later described.
REFERENCES:
patent: 5799209 (1998-08-01), Chatter
patent: 5918074 (1999-06-01), Wright et al.
patent: 6003121 (1999-12-01), Wirt
patent: 6067595 (2000-05-01), Lindenstruth
patent: 6078536 (2000-06-01), Moon et al.
patent: 6085290 (2000-07-01), Smith et al.
patent: 6108758 (2000-08-01), Liu
patent: 6112267 (2000-08-01), McCormack et al.
patent: 6122680 (2000-09-01), Holm et al.
patent: 6138219 (2000-10-01), Soman et al.
Opalka Zbigniew
Pal Subhasis
Ray Rajib
Elamin Abdelmoniem
Lee Thomas
Nexabit Networks, Inc.
Rines and Rines
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