Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-12-30
2002-05-14
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S056000, C711S105000, C711S112000, C711S114000
Reexamination Certificate
active
06389494
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to data storage systems, and more particularly to data storage systems having redundancy arrangements to protect against total system failure in the event of a failure in a component or subassembly of the storage system.
As is known in the art, large host computer systems require large capacity data storage systems. These large computer systems generally include data processors which perform many operations on data introduced to the computer system through peripherals including the data storage system. The results of these operations are output to peripherals, including the storage system.
One type of data storage system is a magnetic disk storage system. Here a bank of disk drives and the computer system are coupled together through an interface. The interface includes CPU, or “front end”, directors (or controllers) and “back end” disk directors (or controllers). The interface operates the directors in such a way that they are transparent to the computer. That is, data is stored in, and retrieved from, the bank of disk drives in such a way that the computer system merely thinks it is operating with one large memory. One such system is described in U.S. Pat. No. 5,206,939, entitled “System and Method for Disk Mapping and Data Retrieval”, inventors Moshe Yanai, Natan Vishlitzky, Bruno Alterescu and Daniel Castel, issued Apr. 27, 1993, and assigned to the same assignee as the present invention.
As described in such U.S. Patent, the interface may also include, in addition to the CPU directors and disk directors, addressable cache memories. The cache memory is a semiconductor memory and is provided to rapidly store data from the computer system before storage in the disk drives, and, on the other hand, store data from the disk drives prior to being sent to the computer. The cache memory being a semiconductor memory, as distinguished from a magnetic memory as in the case of the disk drives, is much faster than the disk drives in reading and writing data.
The CPU directors, disk directors and cache memory are interconnected through a backplane printed circuit board. More particularly, disk directors are mounted on disk director printed circuit boards. CPU directors are mounted on CPU director printed circuit boards. And, cache memories are mounted on cache memory printed circuit boards. The disk director, CPU director and cache memory printed circuit boards plug into the backplane printed circuit board. In order to provide data integrity in case of a failure in a director, the backplane printed circuit board has a pair of buses. One set of the disk directors is connected to one bus and another set of the disk directors is connected to the other bus. Likewise, one set the CPU directors is connected to one bus and another set of the CPU directors is connected to the other bus. The cache memories are connected to both buses. Each one of the buses provides data, address and control information. Thus, the use of two buses provides a degree of redundancy to protect against a total system failure in the event that the directors, or disk drives connected to one bus fail and also increases the bandwidth of the system compared with a system which uses a single bus. One such dual bus system is shown in FIG.
1
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In operation, when the host computer wishes to store end-user (i.e., host computer) data at an address, the host computer issues a write request to one of the front-end directors to perform a write command. One of the front-end directors replies to the request and asks the host computer for the data. After the request has passed to the requesting one of the front-end directors, the director determines the size of the end-user data and reserves space in the cache memory to store the request. The front-end director then produces control signals on either one of the busses connected to such front-end director. The host computer then transfers the data to the front-end director. The front-end director then advises the host computer that the transfer is complete. The front-end director looks up in a Table, not shown, stored in the cache memory to determine which one of the rear-end directors is to handle this request. The Table maps the host computer address into an address in the bank of disk drives. The front-end director then puts a notification in a “mail box” (not shown and stored in the cache memory) for the rear-end director which is to handle the request, the amount of the data and the disk address for the data. Other rear-end directors poll the cache memory when they are idle to check their “mail boxes”. If the polled “mail box” indicates a transfer is to be made, the rear-end director processes the request, addresses the disk drive in the bank, reads the data from the cache memory and writes it into the addresses of a disk drive in the bank. When end-user data previously stored in the bank of disk drives is to be read from the disk drive and returned to the host computer, the interface system operates in a reciprocal manner. The internal operation of the interface, (e.g. “mail-box polling”, event flags, data structures, device tables, queues, etc.) is controlled by interface state data which passes between the directors through the cache memory. Further, end-user data is transferred through the interface as a series of multi-word transfers, or bursts. Each word transfer in a multi-word transfer is here, for example, 64 bits. Here, an end-user data transfer is made up of, for example, 32 bursts. Each interface state word is a single word having, for example, 64 bits.
It is first noted that the end-user data and interface state data are transferred among the directors and the cache memory on the busses. The transfer of each word, whether a burst of end-user data or an interface state data passes through the interface in the same manner; i.e., requiring a fixed amount of overhead, i.e., bus arbitration, etc. Each one of the two busses must share its bandwidth with both end-user data and the interface state data. Therefore, the bandwidth of the system may not be totally allocated to end-user data transfer between the host computer and the bank of disk drives.
SUMMARY OF THE INVENTION
In accordance with the present invention, a data storage system is provided wherein end-user data is transferred between a host computer and a bank of disk drives through an interface. The interface includes a memory and a plurality of directors interconnected through an interface state data bus and a plurality of end-user data busses. At least one front-end one of the directors is in communication with the host computer and at least one rear-end one of the directors is in communication with the bank of disk drives. The interface state data bus section is in communication with: both the at least one front-end one and the at least one rear-end one of the directors; and to the memory. Each one of the plurality of end-user data buses has a first end coupled to a corresponding one of the plurality of directors and a second end coupled to the memory. The plurality of directors control the end-user data transfer between the host computer and the bank of disk drives through the memory in response to interface state data generated by the directors as such end-user data passes through the end-user data busses. The generated interface state data is transferred among the directors through the memory as such end-user data passes through the end-user bus.
With such an arrangement, the system bandwidth is increased because end-user data and interface state data are carried on separate bus systems within the interface.
REFERENCES:
patent: 4780808 (1988-10-01), Moreno et al.
patent: 5206939 (1993-04-01), Yanai et al.
patent: 5586264 (1996-12-01), Belknap et al.
patent: 5603058 (1997-02-01), Belknap et al.
patent: 5742789 (1998-04-01), Ofer et al.
patent: 5787265 (1998-07-01), Leshem
patent: 5799209 (1998-08-01), Chatter
patent: 5805821 (1998-09-01), Saxena et al.
patent: 5819054 (1998-10-01), Ninomiya et al.
patent: 5819104 (1998-10-01), Tuccio
patent: 59480
Castel Daniel
Chilton Kendell Alan
Walton John K.
Daly, Crowley & Mofford LLP
Elamin Abdelmoniem
EMC Corporation
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