System for integrity protection for standard 2n-bit multiple...

Details System for integrity protection for standard 2n-bit multiple... System for integrity protection for standard 2n-bit multiple...

2007-05-29

2010-10-05

Kim, Matt (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S150000, C711SE12103, C714S763000, C714S005110

Reexamination Certificate

active

07809899

ABSTRACT:
An apparatus including a first circuit and a second circuit. The first circuit may be configured to generate one or more command signals, a read data path control signal and one or more write data path control signals in response to an integrity protection control signal and one or more arbitration signals. The second circuit may be configured to write data to a memory and read data from the memory in response to the one or more command signals, the read data path control signal and the one or more write data path control signals. In a first mode, the data may be written and read without integrity protection. In a second mode the data may be written and read with integrity protection, and the integrity protection is written and read separately from the data.

REFERENCES:
patent: 6279072 (2001-08-01), Williams et al.
patent: 2007/0186040 (2007-08-01), Kasahara et al.
patent: 2009/0164712 (2009-06-01), Tanaka et al.

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