System for indicating status of a buffer based on a write addres

Details System for indicating status of a buffer based on a write addres System for indicating status of a buffer based on a write addres

1998-06-12

2000-08-29

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

710 57, 711154, 711156, G06F 1314, G06F 1300, G06F 1200

Patent

active

061122688

ABSTRACT:
A buffer memory control device comprises a buffer memory which is divided into memory areas in cell units each consisting of plural pieces of data by addresses; a write address generation circuit for outputting a write address of the buffer memory; a read address generation circuit for outputting a read address of the buffer memory; a first register for decoding the write address, thereby outputting a flag signal indicating a write address before completion of writing data for each cell; a data decision circuit for deciding presence/absence of cell unit data in the buffer memory and performing read control of the buffer memory on the basis of the flag signal; a second register for decoding the read address, thereby indicating completion of reading data for each cell and outputting a flag reset signal for resetting the flag signal; and an overflow occurrence notification circuit for notifying a transfer source of overflow in the buffer memory on the basis of the flag signal, the data decision circuit performing read control of the buffer memory, and notifying a transfer source that transfer of write data should be aborted before the buffer memory overflows, and data being transferred for each cell, thereby avoiding loss of data.

REFERENCES:
patent: 4692894 (1987-09-01), Bemis
patent: 4975858 (1990-12-01), Ikenoue et al.
patent: 5648777 (1997-07-01), Bays et al.
patent: 5663948 (1997-09-01), Kobunaya

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