Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-10-09
2003-05-20
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06567960
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to circuit simulations, and more particularly to improving circuit simulations by utilizing a simplified circuit model based on effective capacitance and inductance values.
DESCRIPTION OF THE RELATED ART
It has become well accepted that on-chip interconnect delays dominate gate delay in current deep sub-micrometer VLSI circuits. With the continuous scaling of VLSI technology and increased die area, this behavior is expected to continue. In order to properly design complex circuits, more accurate interconnect models and signal propagation characterizations are required.
Historically, on-chip interconnects have been modeled as a single lumped capacitance in the analysis of on-chip interconnects. With the scaling of technology and increased chip sizes, the cross sectional area of wires has been scaled down while on-chip interconnect lengths have increased. The resistance of the on-chip interconnects has increased in significance, requiring the use of more accurate RC delay models. Many design techniques have therefore been developed to minimize the propagation delay of on-chip interconnects. Repeaters are often used to minimize the delay to propagate a signal through those interconnect lines that are best modeled as an RC impedance.
Currently, inductance is becoming more important with faster on-chip rise times and longer wire lengths. Wide wires are frequently encountered in clock distribution networks and in upper metal layers. These wires are low resistive wires that can exhibit significant inductive effects. With these trends, it is becoming more important to include inductance when modeling on-chip interconnects.
Moreover, when the chip operation frequency approaches one (1) Gigahertz or higher, inductance effect becomes significant, especially on global signal lines. Compared to conventional RC line model, the inclusion of inductance, L, can cause thirty (30) percent more delay than the simple RC case. Further, the faster rising time due to inductance effect generates a much larger coupling noise on the neighboring circuits. For these reasons, an accurate RLC line model is important for correct chip design.
Due to the long range coupling characteristics of mutual inductance, a full inductance matrix is usually used in simulation for multiple signal line cases, which increases the simulation time when the number of signal lines is large. More specifically, to minimize global signal line delay with repeater insertion, engineers usually model the multiple signal lines as a single signal line with an effective RC value for the worst case switching impact from the neighboring lines.
In this simplified single line model, a traditionally effective capacitance (Ceff) and an additional effective loop inductance (Leff) are introduced to deal with the condition of the formerly coupled lines. Leff should equivalently represent the extra delay and noise caused by inductance effect. Moreover, the non-linear dependence of inductance coupling with delay should also be taken into account.
With the increasing circuit operation frequency, inductance effects on line delay and signal operation frequency become more important for chip design. Currently, multiple RLC signal lines are modeled by the full self and/or mutual inductance matrix, which is computationally costly and time consuming. Thus, an accurate and efficient on-chip inductance model is necessary for delay estimation and particularly for repeater insertion.
SUMMARY OF THE INVENTION
In accordance with the principles of the present invention, one aspect of the invention pertains to a method of improving circuit simulations. The method includes generating a table of a plurality of effective capacitance values and a plurality of effective inductance values, each effective capacitance value and each effective inductance value being indexed by a respective set of a plurality of interconnect geometry parameters and searching for an effective capacitance value and an effective inductance value in the table based on a set of measured interconnect geometry parameters of the circuit net. The method also includes calculating a delay in response to the effective capacitance value and the effective inductance and simulating the circuit net with the delay.
Another aspect of the present invention relates to a method of modeling a circuit. The method includes determining a portion of the circuit to model and determining a set of interconnect geometry parameters of the portion of the circuit. The method also includes retrieving an effective capacitance value and an effective inductance value for the portion of the circuit based on the set of interconnect geometry parameters being an index value into a table of effective capacitances and inductances and modeling the portion of the circuit as a simplified circuit based on the effective capacitance value and the effective inductance value.
Another aspect of the present invention pertains to a system for improving circuit simulations. The system includes at least one processor, a memory coupled to the at least one processor and a simplified circuit module. The simplified circuit module resides in the memory and is executed by the at least one processor. The simplified circuit module is configured to generate a table of a plurality of effective capacitance values and a plurality of effective inductance values, each effective capacitance value and each effective inductance value being indexed by a respective set of interconnect geometry parameters. The simplified circuit module is also configured to search for an effective capacitance value and an effective inductance value in the table based on a set of measured interconnect geometry parameters of the circuit net and the simplified circuit module is further configured to calculate a delay in response to the effective capacitance value and the effective inductance value. The simplified circuit module is further configured to simulate the circuit net with the delay.
Yet another aspect of the present invention utilizes a computer readable storage medium on which is embedded one or more computer programs. The one or more computer programs implement a method of improving circuit simulations. The one or more computer programs include a set of instructions for generating a table of a plurality of effective capacitance values and a plurality of effective inductance values, each effective capacitance value and each effective inductance value being indexed by a respective set of interconnect geometry parameters. The method also includes searching for an effective capacitance value and an effective inductance value in the table based on a set of measured interconnect geometry parameters of the circuit net and calculating a delay in response to the effective capacitance value and the effective inductance value. The method further includes simulating the circuit net with the delay.
REFERENCES:
patent: 6311313 (2001-10-01), Camporese et al.
patent: 6314546 (2001-11-01), Muddu
patent: 6425117 (2002-07-01), Pasch et al.
patent: 2002/0095646 (2002-07-01), Ohkubo
Cao Yu
Chang Norman
Lin Shen
Nakagawa Osamu Samuel
Xie Weize
Dimyan Magid Y
Hewlett-Packard Development L.P.
Smith Matthew
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