System for improved response time output buffer unit having indi

Details System for improved response time output buffer unit having indi System for improved response time output buffer unit having indi

1996-05-31

1998-11-03

Lee, Thomas C.

Electronic digital logic circuitry

Interface

Current driving

395872, 327333, 327108, 326 27, 326 86, 326121, H03K 190948, G06F 1320

Patent

active

058314504

ABSTRACT:
An output buffer unit for use with a dynamic random access memory includes a first stage for generating complementary logic signals. In an intermediate stage, separate from the generation of the complementary signals, the complementary signals are buffered for application to the output driver stages. By separation of the signal generation stages from the buffering stages, the speed of the logic level-to-logic level transitions can be increased.

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Patent Abstracts of Japan, vol. 11, No. 376 (E-563). 8 Dec. 1987 & JP-A-62 144411 (Hitachi).
IBM Technical Disclosure Bulletin, vol. 30, No. 1, Sep. 1987, New York, US, pp. 1448-1450, XP002019159, "Shift Register Latch Circuit with Predictable Transfer".

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