Patent
1996-04-08
1999-05-18
Lee, Thomas C.
395843, G06F13/00
Patent
active
059059125
ABSTRACT:
The present invention relates to a system and method for implementing peripheral device bus mastering via a general purpose list processor. The system is comprised of four main elements: a bus controller, a DMA controller, a list processor, and a device controller. The system operates under two modes of operation. The two modes arise from the two distinct modules: the DMA controller and the list processor. The first mode of operation is a single buffer transfer mode which is directly compatible with a distributed DMA model. Under this mode, distributed DMA registers within the DMA controller are programmed to transfer a single contiguous buffer of data. The second mode of operation is a multiple buffer transfer mode which uses linked lists of buffer transfer descriptors to program the distributed DMA registers within the DMA controller and initiates transfers independent of software.
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Chambers Peter
Evoy David R.
Goff Lonnie
Story Franklyn H.
Lee Thomas C.
Moy Jeffrey D.
Ton David
VLSI Technology Inc.
Weiss Harry M.
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