System for implementing hardware automated control of burst mode

Details System for implementing hardware automated control of burst mode System for implementing hardware automated control of burst mode

1998-07-20

2000-08-22

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Data transfer specifying

710 33, 710 35, 708655, 708671, G06F 1300

Patent

active

061087238

ABSTRACT:
Burst-mode data transfers between a SCSI host bus adapter and at least one SCSI bus device interface adapter are implemented by hardware. For a first embodiment of the invention, the device interface adapter is equipped with a first, second and third data registers, a comparator, a subtractor, and control logic in the form of an application specific integrated circuit. When a burst-mode transfer is requested, the first register is programmed with a value corresponding to the length of the transfer in bytes, and the second register is programmed with the maximum possible number of bytes in a burst. The comparator then compares the value in stored in the first register with the value stored in the second register and determines which is the smaller. The smaller of the two values is written to the third register. The subtractor then subtracts said third value from said first value to obtain a remainder value. The first value is then replaced with a new first value equal to said remainder value. The control logic orchestrates the steps of comparing said first and second values, storing the smaller of said first and second values in said third register, subtracting said third value from said first value to give a remainder value, replacing said first value with a new first value equal to said remainder value, and causing the steps of comparing, storing, subtracting and replacing to be repeated until said third value is equal to zero. Initial loading of the first and second registers is performed by either the control logic or by a microprocessor. For an alternate embodiment of the invention, the control logic, the comparator and the subtractor are replaced by a microprocessor.

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Universal Serial Bus Specification, Revision 1.0, Chapter 5, pp. 39-83, Jan. 15, 1996.

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