Electrical computers and digital data processing systems: input/ – Input/output data processing – Data transfer specifying
Reexamination Certificate
1998-04-15
2001-02-06
An, Meng-Ai T. (Department: 2783)
Electrical computers and digital data processing systems: input/
Input/output data processing
Data transfer specifying
C710S018000, C710S019000, C710S033000, C710S058000, C710S060000, C711S167000
Reexamination Certificate
active
06185637
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to computer systems which include memory devices that are subject to read and write transactions by a central processing unit (CPU) or other system device. Still more particularly, the present invention relates to a computer system implementation in which data is transferred between memory and the CPU in bursts Still more particularly, the present invention relates to a system in which the burst length of the data stream can be modified based upon a variety of criteria to improve the efficiency of the computer system.
2. Description of the Relevant Art
For most computer systems, the number of clock cycles required for a data access to a memory device depends upon the component accessing the memory and the speed of the memory unit. Most of the memory devices in a computer system are slow relative to the clock speed of the central processing unit (CPU). As a result, the CPU is forced to enter wait states when seeking data from the slower memory devices. Because of the relative slowness of most memory devices, the efficiency of the CPU can be severely compromised. As the operating speed of processors increases and as new generations of processors evolve, it is advantageous to minimize wait states in memory transactions to fully exploit the capabilities of these new processors.
One technique which has been used and which has gained widespread acceptance in computer systems is the use of one or more high speed cache memory devices. Typically, the cache memory is placed intermediate the CPU and system memory, and is used to store frequently used, or recently used, data. While cache memory devices have reduced processor latency times in memory transactions, a problem still exist with latency in memory transactions, especially for memory transactions to other memory sub-systems, such as the system memory.
Another technique which has been used to reduce processor latency in memory transactions is to increase the amount of information transferred in each memory access. Protocols exist for bursting data streams under certain conditions in some systems, such as the PCI (Peripheral Component Interconnect) bus. The PCI bus has a protocol which permits data to be transferred in a burst mode.
The burst mode feature allows reads or writes to consecutive memory locations at high speed, via burst cycles. The normal procedure for reading or writing from memory is that the CPU in a first clock cycle generates the address signals on the address bus, and then in the following clock cycle, data is transferred to or from system memory. Since the PCI data bus, for example, is 32-bits wide, a total of four bytes (each byte has 8 bits) of data can be read or written by the CPU for every two clock cycles. Each set of four bytes transferred on the data bus is referred to as a “double word.” In burst mode, additional sequential double words may be transferred during subsequent clock cycles without intervening address phases. For example, a total of four double words can be read into the CPU using only five clock cycles because only the starting address is sent out on the address bus, and subsequently the first double word of data is read during the second cycle, the next double word of data during the third cycle, and so on. Thus, where a normal transfer of four double words would take at least eight clock cycles, the burst mode permits four doublewords to be transferred in five clock cycles. Burst mode operation thereby accommodates relatively high data transfer rates, and significantly reduces the latency involved in a memory transfer.
Despite the advantages of operating in burst mode, the burst mode feature has certain limitations. One limitation inherent in burst mode transfers is that the burst mode length typically is fixed, and cannot be altered. In addition, the burst mode feature is not responsive to actual latency conditions in the system. In the devices and busses which use burst mode transactions, the burst length typically is fixed by the system designer. The optimal burst length value, however, is dependent upon a number of factors that typically are not known during the design process. Consequently, a system designer does not have all of the information necessary to make a fully informed decision regarding the optimal burst length for a particular memory device.
SUMMARY OF THE INVENTION
The present invention solves the shortcomings and deficiencies of the prior art by providing a computer system that includes a bus interface unit (also referred to as “BIU”) to orchestrate data accesses between memory devices and a central processing unit (CPU) core. Preferably, the BIU includes a register with a dedicated bit to indicate whether the adaptive burst mode feature is to be implemented by the BIU. The bus interface unit preferably includes a table of historical data on the latencies experienced for different memory regions. A second table also preferably is provided which indicates an optimal burst length for particular latency periods (which may be measured by WAIT states, or other criteria). The optimal burst length for a latency period can be fixed by the system designer, or can be modified during system operation by a programmer or through a self-executing algorithm. The table of historical data preferably is accumulated by the bus interface unit based on observations of signals appearing on the CPU local bus and system bus. When a particular access then is routed through the bus interface unit to a particular memory range, the BIU implements a burst mode transfer with a burst length specified in the look-up table.
The actual implementation of the burst transfer may be made through the use of a BURST control signal. According to this embodiment, the memory continues burst data to as long as the BURST line remains asserted by the BIU. When the BURST line is deasserted, the target memory unit completes the burst transaction. The BIU determines how long to assert the BURST signal based upon the look-up table. Alternatively, the length of the burst data transfer may be indicated by signaling between the BIU and target memory device prior to the time that the memory device drives out the desired data. In this embodiment, the BIU could indicate to the memory device that a burst data transfer is desired, and the memory device could respond with the expected response time, from which the BIU determines the optimal burst length.
The historical data to be monitored preferably includes WAIT states, which define the length of time between the initiation of a memory transaction and the response of the first data item from the targeted memory device. The BIU then stores, as a running count of clock signals, the WAIT period. In the preferred embodiment, the BIU stores the WAIT periods on an address range basis. Alternatively, the WAIT periods (or other latency measurement) can be stored on a component by component basis. The look-up table preferably includes x bits to define the address range, y bits to define the latency period, and z bits to define the optimal burst length.
In addition to the WAIT periods, the BIU also may look at other criteria when assigning the optimal burst length. For example, the BIU can monitor the number of accesses to a memory range within a predetermined period as an indication of whether to increase the length of the data transfer. Other criteria which can be monitored by the BIU include (1) the internal state of the CPU, such as pending load, fetch, and store requests; (2) historical data regarding previous execution history; (3) the content of memory responses; and (4) the current state of any CPU special mode bits.
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Hack Norm M
Strongin Geoffrey S. S.
Advanced Micro Devices , Inc.
An Meng-Ai T.
Conley Rose & Tayon PC
El-Hady Nabil
Kivlin B. Noäl
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