System for idling a processor pipeline wherein the fetch...

Details System for idling a processor pipeline wherein the fetch... System for idling a processor pipeline wherein the fetch...

2007-09-04

2007-09-04

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Computer power control

C713S320000, C710S059000

Reexamination Certificate

active

10963159

ABSTRACT:
A processor disclosed herein comprises a clock configured to drive clock signals and a processor pipeline having a plurality of stages. The processor includes processor idling circuitry, which is configured within the stages and is responsive to an idle_request signal. A first stage comprises a device for stopping incoming instruction values from being further processed when the idle_request signal is received. Also, at least two of the remaining stages comprise idle_flag logic configured to receive the idle_request signal, the idle_flag logic further configured to transmit an idle_flag through the processor pipeline.

REFERENCES:
patent: 6247134 (2001-06-01), Sproch et al.
patent: 6636976 (2003-10-01), Grochowski et al.
patent: 2003/0070013 (2003-04-01), Hansson

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