Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
1999-08-06
2002-11-05
Gaffin, Jeffrey (Department: 2782)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S033000, C710S035000, C710S055000
Reexamination Certificate
active
06477592
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to the field of semiconductor integrated circuits, and more particularly, to input/output interfacing for a semiconductor chip.
BACKGROUND OF THE INVENTION
Data input into or output from an integrated circuit (IC) device is represented by a sequence of varying voltage values appearing in an appropriate signal. For data that is output from an IC device, the voltage level for a logical “0” (logic-0) is generally referred to as “voltage output low” or “V
OL
,” while the voltage level for a logical “1” (logic-1) is generally referred to as “voltage output high” or “V
OH
.” For data that is input into an IC device, the voltage level for a logic-0 is generally referred to as “voltage input low” or “V
IL
,” while the voltage level for a logic-1 is generally referred to as “voltage input high” or “V
IH
.”
For the signals which communicate data to and from an IC device, a reference voltage (V
REF
) may define how the sequence of voltage values in each signal should be interpreted or construed in order to derive the represented data. Furthermore, suitable margins above and below the reference voltage are provided for interpretation of the signals.
Various industry-standard, interface signaling technologies have been developed for transmitting data to and from an IC device. These signaling technologies include transistor-to-transistor logic (TTL), low-voltage TTL (LVTTL), stub-series terminated logic (SSTL_
3
or SSTL_
2
), and RAMBUS signaling level (RSL).
The logic-0 (V
IL
and V
OL
) and logic-1 (V
IH
and V
OH
) voltage levels are different for each interface signaling technology. TTL and LVTTL have relatively large signal swings and do not require a reference voltage to determine whether the data under transfer is either a logic-0 or a logic-1. SSTL_
2
, SSTL_
3
and RSL have smaller signal swings (0.8-1.2 volts) for high speed data transfer, and require a reference voltage for interpreting data. RSL utilizes an open-drain output driver with external pull-up termination resistor connected to a termination voltage V
TT
. The following chart provides values for the voltage levels of the various interface signaling technologies.
VIH
VIL
VOH
VOL
VREF
VTT
VDDQ
TTL
2.4 V
0.8 V
2.4 V
0.8 V
N/A
N/A
5 V
LVTTL
2.0 V
0.8 V
2.0 V
0.8 V
N/A
N/A
3.3 V
SSTL-3
VREF +
VREF −
VTT +
VTT −
1.5 ±
1.5 ±
3.3 V
0.4 V
0.4 V
0.6/0.8 V
0.6/0.8 V
0.2 V
0.05 V
SSTL-2
VREF +
VREF −
VTT +
VTT −
1.25 ±
VREF ±
2.5 V
0.35 V
0.35 V
0.57/
0.57/0.76 V
0.1 V
0.04 V
0.76 V
RSL
1.8 V
1.0 V
1.8 V
1.0 V
1.4 V
1.8 V
2.5 V
Note:
(1) All numbers listed in the chart above are typical values.
(2) VDDQ is the power supply for data output driver.
The use of a reference voltage (V
REF
) to determine the logic level of data with some interface signaling technologies (i.e., those having a small signal swing) presents many disadvantages. For example, a number of different factors—such as varying internal supply voltage or reference voltage, or noise created at one or more voltage drivers—can cause the value of the signal levels (e.g., V
OH
, V
OL
, V
IH
, V
IL
) to drift or change. This results in a loss of signal margin during operation, which ultimately can lead to problems with data integrity. Furthermore, with previously developed interface technologies, the signal levels of logic-1 and logic-0 are not scaleable. This sets constraints on the bandwidth of data transfer. Also, because signal levels are not scalable, the interface technologies are plagued with high power consumption and significant switching noise. This in turn causes problems in designing systems in which semiconductor integrated circuits with different electrical I/O interface specifications are used, due to the scaling down of design rules and lithography of the integrated circuits. In addition, previously developed interface technologies utilize a high data slew rate that causes electromagnetic interference (EMI) problem, especially when a wider data bus is desirable to meet the bandwidth requirements of a high performance system. Accordingly, it is difficult to achieve appropriate data setup and hold times for high data rate operation.
SUMMARY OF THE INVENTION
The disadvantages and problems associated with previously developed interfaces for an integrated circuit device have been substantially reduced or eliminated using the present invention.
According to the present invention, a correlated double-sampling (CDS) technique is provided for the input and output of data in a semiconductor chip. For each element (e.g., bit) of data in an outgoing data stream, the technique adds a separate reference element. The data elements and respective reference elements are represented by corresponding voltage values in a transmission signal output by the semiconductor chip. When the transmission signal is received by another semiconductor chip, it is sampled for both the data elements and the respective reference elements—hence, the term “double-sampling”. Each reference element is used to interpret the corresponding data element so that the data element can be recovered. For example, in one embodiment, the data element may be compared against the respective reference element.
An input/output (I/O) interface circuit, according to one embodiment of the present invention, implements the CDS technique. For output from a semiconductor chip, the CDS I/O interface circuit adds a reference element for each data element in an outgoing data stream. The CDS I/O interface circuit generates a transmission signal in which the data elements and respective reference elements are represented by corresponding voltage values. The transmission signal is sent out from the semiconductor chip. For input into the semiconductor chip, the CDS I/O interface circuit receives a transmission signal wherein various voltage values represent a number of data elements and respective reference elements. The CDS I/O interface circuit samples the received signal for the data elements and reference elements. The CDS I/O interface circuit interprets each data element using the respective reference element.
In accordance with one embodiment of the present invention, an I/O interface circuit for a semiconductor chip is provided. The I/O interface circuit includes an output buffer circuit and an input buffer circuit. The output buffer circuit can receive a first stream of data elements for output from the semiconductor chip, add a separate reference element for each data element in the first stream, and generate a first data transmission signal representing the data elements of the first stream and the respective reference elements. The input buffer circuit can receive a second data transmission signal representing data elements of a second stream and respective reference elements for the data elements of the second stream, sample the second data transmission signal to obtain voltage values for each data element of the second stream and the respective reference element, and interpret the voltage value for each data element of the second stream against the voltage value for the respective reference element in order to recover the data elements of the second stream.
In accordance with another embodiment of the present invention, a method for interfacing between a first semiconductor chip and a second semiconductor chip includes the following steps: receiving a stream of data elements for output from the first semiconductor chip; adding a separate reference element for each data element in the stream; generating a data transmission signal representing the data elements of the stream and the respective reference elements; transmitting the data transmission signal out of the first semiconductor chip; receiving the data transmission signal at the second semiconductor chip; sampling the data transmission signal to obtain voltage values for each data element of the data stream and the respective reference element; and interpreting the voltage value for each data element of the s
Chang Shuen-Chin
Chen Jawji
Ng Cindy Yuklin
Park Yong E.
Tung Chiayao S.
Gaffin Jeffrey
Integrated Memory Logic, Inc.
Perveen Rehana
Skjerven Morrill LLP
Woo Philip W.
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