System for handling parallel input/output threads with cache...

Details System for handling parallel input/output threads with cache... System for handling parallel input/output threads with cache...

2009-04-14

2011-10-11

Chen, Alan (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output access regulation

C710S005000, C710S052000, C710S058000, C711S100000

Reexamination Certificate

active

08037219

ABSTRACT:
A system comprising a scheduler, a first core, and a second core. The scheduler may be configured to prioritize a plurality of input/output (IO) requests. The first core may be configured to process one of the plurality of IO requests based on the prioritizing of the plurality of IO requests. The second core may be configured to process a different one of the plurality of IO requests based on the prioritizing of the plurality of IO requests.

REFERENCES:
patent: 5313584 (1994-05-01), Tickner et al.
patent: 2010/0250785 (2010-09-01), Shin et al.

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