Electrical computers and digital processing systems: processing – Processing control
Reexamination Certificate
1999-02-04
2003-02-11
Maung, Zarni (Department: 2154)
Electrical computers and digital processing systems: processing
Processing control
C712S221000, C712S222000, C712S223000, C712S227000, C714S025000, C714S048000, C714S722000, C708S495000, C710S262000
Reexamination Certificate
active
06519694
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates generally to the handling of load errors in computer processors, more especially but not exclusively to the handling of load errors resulting from speculative loads.
For good performance of a processor in a data processing system it is desirable to overlap data loads with other operations, by moving the load instructions forward to earlier positions in the instruction stream. When a load instruction is moved ahead of conditional control structures in the program flow, then the address it reads from may not yet be validated by the rest of the program code and may therefore be wrong. Loading of this kind is referred to as speculative.
A speculative load is thus defined a load operation that is issued by a processor before it is known whether the results of the load will be required in the flow of the program. Speculative loads can reduce the effects of load latency by improving instruction scheduling. Generally, speculative loads are generated by the compiler promoting loads to positions before test control instructions.
Speculative loads are often implemented as non-faulting loads. A non-faulting load is a load which always completes, even in the presence of faults. The semantics of a non-faulting load are the same as for any other load, except when faults occur. An example of a fault is an address-out-of-range error. When a fault occurs, it is ignored and the hardware and system software cooperate to make the load appear to complete normally, but in some way to return the result in a form which reflects that the loaded datum is invalid. Typically, the hardware will be configured to generate a fault indication for a failed normal load and to return a particular data value for a failed speculative load.
One known example of the handling of a failed load is the standard use of a poison bit or valid bit in the register into which the result of the speculative load is loaded. If the non-faulting load is successful then the poison bit remains unset or the valid bit is set. On the other hand, if the non-faulting load is unsuccessful then the poison bit is set or the valid bit remains unset. The software or hardware is then configured to ensure that any subsequent use of the data in the register generates a trap. With this approach, whenever there is an error in a non-faulting load, the program flow will enter into an error handling routine when an operation on the invalid data is attempted.
Another example of the handling of a failed load is to be found in the Sun SPARC processors UltraSPARC I & II. Here a non-faulting load returns zero-valued data when an exception (i.e. an error) is encountered. Software code then uses a compare instruction to check the load result before use, not using the speculatively loaded data if it is zero. If the result is zero, then the memory address is read again later using a normal (non-speculative) load to which normal protection mechanisms apply. The normal load will be able to differentiate between correct zero-valued data and an exception condition. Only if the normal load shows an error will an exception be caused, i.e. a trap generated. With this approach, whenever a zero result is returned from a non-faulting, speculative load, the instruction stream is stalled until the normal load has completed.
It is an aim of the invention to provide a mechanism for handling non-faulting loads which can improve program flow in the cases that non-faulting loads return invalid results.
SUMMARY OF THE INVENTION
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Features of the dependent claims may be combined with those of the independent claims as appropriate and in combinations other than those explicitly set out in the claims.
According to a first aspect of the invention there is provided a processor comprising a load/store unit, a register unit comprising a set of registers and an arithmetic logic unit, the processor being of the kind in which the load/store unit has an error flag for marking as invalid a datum loaded to the load/store unit following a load which has not reliably completed and which is thus to be treated as having failed. The processor is modified by the provision of a symbolic entity transmitter operatively arranged as an output stage of the load/store unit so that a symbolic entity is loaded into a destination one of the registers or directly into the arithmetic logic unit when the error flag is set in the load/store unit following a failed load. Moreover, the arithmetic logic unit is configured to propagate the symbolic entity, when present in an operand of an operation carried out by the arithmetic logic unit, to a result of the operation, the result with symbolic entity then being conveyed either to a destination register of the register unit or the load/store unit, depending on the processor design.
In the present document, it should be noted that the term arithmetic logic unit (ALU) is used as a generic term for both integer logic units (which in the art are usually referred to as arithmetic logic units) and floating point units (FPUs).
In the case of floating-point registers in a processor conforming to IEEE 754, the symbolic entity may be a Not-a-Number (NaN) value. The symbolic entity transmitter may then take the form of a bit pattern generator interposed between the load/store unit and the register unit, and/or between the load/store unit and the ALU. The bit pattern generator is then configured and arranged to load a bit pattern of a NaN value into the load destination register or the ALU in the case of a failed load. The NaN value may be one of the large number of defined NaN values which is not used as a NaN value by the remaining hardware. Alternatively, a NaN value used by the processor for other purposes may be used. No or minimal special hardware is required in the ALU, since the ALU will automatically propagate a NaN value through arithmetic and logical operations. Moreover, no additional internal bandwidth will be required for the communication links between the load/store unit, register unit and ALU, since the failed load information is conveyed with the normal data bits.
Thus, according to a floating-point aspect of the invention, there is provided a bit pattern generator operatively arranged in an output path from the load/store unit so that a Not-a-Number value for the invalid datum is loaded into a destination one of the floating-point registers in the register unit, or directly into the ALU.
The ALU is preferably configured to propagate the Not-a-Number value as a Quiet-Not-a-Number (QNaN) value through operations carried out in the ALU. Moreover, the QNaN value is preferably testable for in a datum by a system software command code provided for that purpose. The command code may include a conversion, conditional on the test result, of the QNaN value to a Signaling-Not-a-Number (SNaN) value, so as to cause generation of a trap on subsequent use of the datum concerned. This may be especially useful in a processor supporting multiple threads of control where much of the processor execution will involve computing alternative “ways” only one of which will ultimately lie on the execution path of the code. Alternatively, the command code may include a conditional branch, conditional on the test result, for immediately invoking an error handling routine for dealing with the invalid datum.
In the case of integer registers, the symbolic entity transmitter may take the form of hardware interposed between the output-side of the load/store unit and the input-side of the register unit and/or ALU so that, in the case of a failed load, the error flag set in the load/store unit is conveyed to set or unset a poison or valid bit, respectively, in the destination register or operand of the ALU. Moreover, the ALU and register unit, or ALU register unit and load/store unit, are interconnected so as to transmit and receive the poison or valid bit from each other during processor operation, and the ALU is internally config
Kivlin B. Noäl
Lin Wen Tai
Maung Zarni
Sun Microsystems Inc.
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