Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
1998-04-17
2002-12-17
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C711S170000, C711S173000, C710S040000, C712S005000, C712S224000
Reexamination Certificate
active
06496916
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the partitioning of memory. More particularly, it relates to an efficient and flexible paging technique for memory.
2. Background of Related Art
Large blocks of data memory are often used by more than one operating software program and/or by more than one running copy of the same program. Conventionally, the data memory is partitioned to allow the separate programs to use separate portions of the memory.
For instance, when running multiple programs (or sessions) of an application such as a modem on a digital signal processor (DSP), the data memory space is conventionally partitioned among the various program sessions. In this way, each independent program session will independently access a unique portion of the data memory space.
Two conventional techniques are known for partitioning data memory among multiple operating programs: fixed length paging and memory address offset.
Fixed length paging partitions the entire data memory into equal length blocks of memory, typically in lengths equal to a power of 2 (e.g., 8 K, 16 K, 32 K, etc.). According to known paging techniques, a number of the most significant bits p of the accessing address (e.g., from a processor) are replaced by a page number stored in a register pre-written by the software application. In this case, the page number is related to a separated data buffer, and the non-changed (i.e., the least significant) bits of the accessing address a represent addressing within the selected page or data buffer inside the buffer.
FIG. 9
shows a conventional data memory
650
partitioned into four pages 600-603. Each of the four pages 600-603 has an equal length. For instance, if the total data memory space is 64 K, then each page 600-603 is 16 K in length.
Fixed memory paging is fast because address bits from the page number register and processor are merely combined (not added), but is limited because the page lengths are fixed throughout the total length of the data memory. Thus, only 2
p
pages (or data buffers) can be partitioned in data memory, each having a fixed length 2
a
, wherein the superscript p refers to the number of most significant bits p of the accessing address (e.g., from a processor) which are replaced by a page number stored in a register pre-written by the software application, and the superscript a refers to the number of least significant address bits from the processor used for addressing purposes. Because of the fixed length nature of the pages or data buffers, unused portions of the pages of the data memory are unusable by other programs and thus wasted.
A more efficient conventional technique for partitioning data memory is memory address offset. Memory address offset schemes use a memory offset value and an address adder which adds a pre-written memory offset value to each data memory access address.
Memory address offset is shown in FIG.
10
. The data memory
650
is partitioned into variable length portions by offset values
701
-
705
, forming, e.g., six data buffers
710
-
715
in the disclosed example. The offset values
701
-
705
may have any value within the range of the data memory.
Memory address offset techniques are very flexible because the data buffers
710
-
715
may be any length. However, the process of adding the relevant one of the address offset values
701
-
705
to every data memory address access to the data memory
650
significantly slows down the memory access time because the offset is added “on-the-fly” to each data memory address. Thus, the actual access to the data memory is delayed with respect to the original data memory address. This delay is related to the size of the adder and can be, e.g., up to 10 nanoseconds (nS) for 0.35 micrometer (&mgr;m) technology.
There is a need to improve the partitioning of data memory in a way which makes efficient use of the available data memory space and which does not increase access time to the data memory.
SUMMARY OF THE INVENTION
In accordance with the principles of the present invention, a memory partitioning module comprises a memory paging register to partition a memory into a plurality of partitions. A memory paging mask register is adapted to disable at least one bit in the memory paging register.
In accordance with another aspect of the present invention, a memory partitioning module comprises a memory paging register adapted to define a plurality of memory pages in a memory. A memory paging mask register combines at least two of the memory pages to effectively create a larger memory page.
A method of partitioning memory in accordance with the principles of the present invention partitions a block of memory into a plurality of equal length pages. A subplurality of the equal length pages are combined to provide a plurality of unequal length data buffers in the block of memory.
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Fadavi-Ardekani Jalil
Fitch Kenneth D.
Sindalovsky Vladimir
Agere Systems Inc.
Bollman William H.
Namazi Mehdi
Yoo Do Hyun
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