System for facilitated analysis of PCI bus malfunction

Details System for facilitated analysis of PCI bus malfunction System for facilitated analysis of PCI bus malfunction

2006-02-21

2006-02-21

Baderman, Scott (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S056000, C714S057000, C710S109000, C710S117000

Reexamination Certificate

active

07003701

ABSTRACT:
In a computer system, which makes an error detectable in case plural PCI target devices respond in one PCI cycle and the PCI protocol has become illicit, a processor1is connected over a PCI bus10to plural PCI devices a100to d130,each of which activates corresponding target operating signal a20to d50respectively when operating as a PCI target device. The PCI bus monitor circuit200monitors the target address of a command executed on the PCI bus10and the target operating signals a20to d50from the plural PCI devices a100to d130.If plural PCI target devices have responded for one PCI cycle, the PCI bus monitor circuit200sends an error report signal210to the processor unit1.

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Japanese Office Action dated Oct. 13, 2004 (with partial English translation).

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