System for executing, canceling, or suspending a DMA transfer ba

Details System for executing, canceling, or suspending a DMA transfer ba System for executing, canceling, or suspending a DMA transfer ba

1997-08-08

1999-10-26

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

710 22, 710 36, 710 40, G06F 1330

Patent

active

059744790

ABSTRACT:
A data processing device having a DMA function for controlling DMA transfer, comprises a DMA unit, a CPU, a bus arbitration unit for controlling bus-using right of the DMA unit or the CPU, and an interruption controller for supplying an interruption request signal. The DMA unit includes a register, a comparator for making a comparison between a priority of a DMA transfer and a priority set on an interruption request, and a sequencer for deciding whether the DMA transfer is to be executed, canceled, or suspended in the operation state of a DMA unit according to the comparison result of the comparator.

REFERENCES:
patent: 3421150 (1969-01-01), Quosig et al.
patent: 5493646 (1996-02-01), Guttag et al.
patent: 5619726 (1997-04-01), Seconi et al.
patent: 5664200 (1997-09-01), Barlow et al.
patent: 5666364 (1997-09-01), Pierce et al.
Translation of Japanese Patent Office Office Action dated Sep. 8, 1998.

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