System for estimating a terminal capacitance and for...

Details System for estimating a terminal capacitance and for... System for estimating a terminal capacitance and for...

2006-10-25

2009-11-03

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07614023

ABSTRACT:
A method for estimating a terminal capacitance associated with a terminal of a cell of a digital circuit includes providing first and second capacitance values associated with an upper and lower bound, respectively, on the terminal capacitance, providing results of a timing analysis of the digital circuit, and determining an estimation value for the terminal capacitance based on the results of the timing analysis and at least one of the first and second capacitance values. A system for estimating a terminal capacitance includes a storage unit which stores the first and second capacitance values and a processor which performs a timing analysis of the digital circuit and determines an estimation value for the terminal capacitance based on the timing analysis and at least one of the first and second capacitance values.

REFERENCES:
patent: 7114142 (2006-09-01), Segal et al.
patent: 2005/0131661 (2005-06-01), Lang et al.
patent: 2005/0232066 (2005-10-01), Ishibashi et al.
patent: 2005/0283750 (2005-12-01), Kosugi et al.
patent: 2006/0095869 (2006-05-01), Levy
patent: 0 223 586 (1986-05-01), None
patent: 0 204 178 (1986-12-01), None
patent: 2001167143 (2001-06-01), None

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