System for end of interrupt handling

Details System for end of interrupt handling System for end of interrupt handling

2006-05-30

2006-05-30

Ray, Gopal C. (Department: 2111)

Electrical computers and digital data processing systems: input/

Interrupt processing

C710S048000, C710S269000

Reexamination Certificate

active

07054974

ABSTRACT:
An interrupt controller includes circuitry to process at least one end of interrupt (EOI) vector, the circuitry being capable of substantially simultaneously comparing the at least one EOI vector with a plurality of interrupts.

REFERENCES:
patent: 5506997 (1996-04-01), Maguire et al.
patent: 5555420 (1996-09-01), Sarangdhar et al.
patent: 5727217 (1998-03-01), Young
patent: 5771387 (1998-06-01), Young et al.
patent: 5918057 (1999-06-01), Chou et al.
patent: 6192442 (2001-02-01), Haren et al.
patent: 6298410 (2001-10-01), Jayakumar et al.
patent: 6754754 (2004-06-01), Quach et al.
patent: 2001/0052043 (2001-12-01), Pawlowski et al.
patent: 2002/0087775 (2002-07-01), Looi et al.
“a client-based scheduling algorithm for Web proxy clusters” by Narlikar et al. (abstract only) Publication Date: Apr. 4-6, 2001.
Intel 82093AA I/O Advanced Programmable Interrupt Controller (IOAPIC) Specification, 20 pages.
Espasa, M., Valero, M., and Smith, J.E., “Out-of order vector architectures”, Abstract only, Dec. 1997, 2 pages.

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