System for efficient implementation of multi-ported logic FIFO s

Details System for efficient implementation of multi-ported logic FIFO s System for efficient implementation of multi-ported logic FIFO s

1997-06-25

2000-04-25

Yoo, Do Hyun

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

710 52, G06F 1202

Patent

active

060556161

ABSTRACT:
A system and method for efficient implementation of a multi-port logic first-in, first-out ("FIFO") structure or particular utility in high clock speed integrated circuit ("IC") processor design which provides for reduced on-chip area requirements and fewer and less timing critical electrical interconnect paths. The advantageous reduction in IC area and enhanced performance disclosed herein is enabled through the rotation of the inputs and outputs of the FIFO; maintenance of decoded head and tail pointers, and folding the FIFO entry locations such that the entries are arranged in an interleaved fashion.

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