Computer graphics processing and selective visual display system – Computer graphics display memory system – Multi-port memory
Reexamination Certificate
1998-12-23
2001-10-23
Tung, Kee M. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Multi-port memory
C345S539000, C365S230050
Reexamination Certificate
active
06307565
ABSTRACT:
FIELD OF THE INVENTION
This system relates generally to memory for raster-scanned displays and, in particular, to a system for controlling the reading from and writing to memory used as a buffer for asynchronously received digital video data to be displayed on an LCD display.
PROBLEM
Typically, a raster scanned display is synchronized to the incoming digital video to be displayed. When digital video is received for display on a raster scanned display device asynchronously with respect to the display frame read rate, the incoming video must be buffered. The video can then be read out of the buffer synchronously with respect to the display. The types of memory schemes typically employed for this buffering are described below, including dual-port memory, ‘ping-pong’ memory, and ‘ping-pong-pong’ memory configurations.
A dual-port (RAM) memory allows the simultaneous writing and reading of data. Dual-port memories simplify many data buffering schemes in that they do not require the complex multiplexing of address and data buses needed by memory configurations such as the ‘ping-pong’ and ‘ping-pong-pong’ buffering schemes (described below). However, in a typical system which uses a raster scanned display, such as an LCD display, the incoming video signal is asynchronous with respect to the LCD frame read rate. Therefore, absent some method of compensating for the difference in the read and write rates, the write and read addresses in LCD memory must eventually cross each other. This crossover will occur because the incoming video data is filling a raster scanned video frame either faster or more slowly than the LCD frame display rate. When such address crossover occurs, the LCD will display part of the new incoming video frame and part of the last incoming video frame. When the video image contains motion, this split becomes visible on the display, since part of the screen shows a segment of the image in the prior frame, and part of the screen shows a segment of the current image, which typically has moved relative to the prior frame. If the incoming video frame rate is close to the displayed frame rate, this frame split can remain static on the LCD for many frames or slowly move across the screen. Such a frame split may cause the LCD display image to be significantly degraded in real-time applications such as flight navigation or monitoring of other time-critical functions.
A ‘ping-pong’ memory allows data to be written to a ‘ping’ buffer while data is read from a ‘pong’ buffer. At the completion of each frame, the ‘ping’ and ‘pong’ buffers are swapped. One of the problems with using this system with asynchronous reads and writes is similar in effect to that of a dual-port memory configuration. Since the incoming video frame is not matched to the LCD video read-out, the buffer swapping will cause part of an old frame to be displayed at the same time that part of a new frame is being displayed.
Similar to the ‘ping-pong’ memory arrangement described above, a ‘ping-pong-pong’buffering scheme allows data to be written to a ‘ping’ buffer while data is read from either of two ‘pong’ buffers. When either the write or read operations are complete for a given frame, the operations then proceed to use the idle buffer for the next frame. This prevents the write and read addresses from ever crossing. Problems with this scheme include the added expense of having three banks of full field memory, the increased circuit board area used and the difficulty of multiplexing the address and data buses between the video input and output and the three banks of memory.
SOLUTION
The above problems of address crossover, address and data multiplexing, as well as added cost and circuit board area are resolved by the system of the present invention, which utilizes a dual-port ‘ping-pong’ (dual buffer) memory configuration to buffer digital video received for display on a raster scanned screen asynchronously with respect to the screen display rate. In accordance with the present invention, the incoming video is switched between ‘ping’ and ‘pong’ buffers for each successive incoming frame of video data. The video output to the raster scanned display is also switched between the ‘ping’ and ‘pong’ buffers for each video frame, provided the address locations of the incoming video being written and the output video being read are sufficiently far apart. If the address locations are closer than a minimum number of display lines, the video output does not switch buffers but repeats the display read operation from the same buffer again. In this way, the write and read addresses are separated by an entire bank of memory and never cross. Assuming that the incoming video data rate is not exactly the same as the scanned display rate, the addresses will again creep closer together and eventually a frame read operation will need to be repeated.
REFERENCES:
patent: 5130979 (1992-07-01), Ohtawa
patent: 5247485 (1993-09-01), Ide
patent: 5255220 (1993-10-01), Filliman
patent: 5914711 (1999-06-01), Mangerson et al.
Hancock William Ray
Quirk Robert John
Honeywell International , Inc.
Tung Kee M.
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