System for determining the average latency of pending pipelined

Details System for determining the average latency of pending pipelined System for determining the average latency of pending pipelined

1997-09-09

1999-07-06

An, Meng-Ai T.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714 37, 714 39, 714 47, 714 48, G06F 1100

Patent

active

059192682

ABSTRACT:
Logic for determining the average latency of pending pipelined and split bus transactions within a computer system including a bus, such as an Intel Pentium Pro or P6 bus, which supports pipelined and split bus transactions. The logic includes a first counter connected to the bus, and containing a TOTAL QUALIFIED CYCLES count value which is incremented on the start of every qualified bus cycle placed on the bus; logic for determining a cycle COUNT-BY-VALUE representing the number of outstanding or pending qualified bus cycles during any bus cycle; and a second counter which is incremented at the start of every qualified bus cycle occurring during the sample period by the number of outstanding qualified bus cycles to provide a TOTAL LATENCY CLOCKS count value. Divider logic is connected to receive the TOTAL QUALIFIED CYCLES count value from the first counter and the TOTAL LATENCY CLOCKS value from the second counter and divide the TOTAL QUALIFIED CYCLES count value into the TOTAL LATENCY CLOCK value to determine the average number of clocks of latency, or average number of pending bus cycles, per qualified bus cycle.

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Sarangdhar, "An overview of the Pentium Pro processor bus", Compcon '96 Technologies for the Information Superhighway Digest of papers, pp. 383-387, Feb. 1996.
Papworth, D.B., "Tuning the Pentium Pro microarchitecture", IEEE Micro, pp. 8-15, Apr. 1996.

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