System for determining status of errors in a memory subsystem

Details System for determining status of errors in a memory subsystem System for determining status of errors in a memory subsystem

1988-12-21

1990-10-16

Smith, Jerry

Excavating

371 216, 371 212, 371 51, G06F 1110

Patent

active

049641301

ABSTRACT:
A system and method for detecting an error that occurred in a multi-chip memory storage device in a data processing system. The system detects an error and receives data and check bits associated therewith. A process that uses the principle of scrubbing and incorporates high speed error flags distinguishes between hard and soft errors.

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F. Aichelmann, "Syndromes for Error Location Mapping of Memory Arrays", IBM TDB, vol. 26, No. 6, 11/1983, pp. 2749-2750.

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