System for detecting and reporting defects in a chip

Details System for detecting and reporting defects in a chip System for detecting and reporting defects in a chip

2005-11-15

2005-11-15

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06966042

ABSTRACT:
Under the present invention, each of a set of functional chiplets in a chip includes an error condition staging system and a trap condition control system. The error condition staging system includes error condition combinational logic that detects a set of error conditions, and a set of error condition registers that store data related to the set of error conditions. The data in the set of error condition registers is communicated to an output multiplexor, which is controlled by a trap signal outputted from the trap condition control system. An error condition signal containing the data is outputted from the output multiplexor and is received by an operational chiplet. The operational chiplet also receives clock signals from a clock controller pertaining to each functional chiplet. Based on the error condition signals and the clock signals, the operational chiplet reports any defects in the functional chiplets to a host processor.

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