Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2003-10-24
2010-02-23
Patel, Niketa I (Department: 2181)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C341S010000, C341S096000, C341S097000, C377S033000, C377S034000, C707S793000, C710S057000, C711S217000, C711S219000
Reexamination Certificate
active
07668983
ABSTRACT:
Systems and methods for designing data structures are provided. In one embodiment, an asynchronous first-in-first-out (FIFO) data structure may include, for example, a FIFO memory having a depth d in which d is an integer and a code generator coupled to the FIFO memory. The code generator may provide, for example, a first code sequence of length 2d. The first code sequence may have a circular property and a Hamming length of one for any two consecutive codes of the first code sequence. The first code sequence may be generated from a second code sequence by removing one or more pairs of mirrored codes of the second code sequence.
REFERENCES:
patent: 6337893 (2002-01-01), Pontius
patent: 6553448 (2003-04-01), Mannion
patent: 6703950 (2004-03-01), Yi
patent: 6810468 (2004-10-01), Miyamoto et al.
Broadcom Corporation
Franklin Richard
McAndrews Held & Malloy Ltd.
Patel Niketa I
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