Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Counting – scheduling – or event timing
Reexamination Certificate
2000-09-06
2004-03-02
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Counting, scheduling, or event timing
C714S047300, C714S025000, C714S037000, C714S010000
Reexamination Certificate
active
06701447
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to a method and structure for managing counter events by providing a means for delaying the processing of a counter event until the event can be processed by computer system resources. In even more particular aspects, this invention relates to managing the counting of a large number of individual events in a computer network system with large counter arrays where large volumes of information are being passed, such as, for example, in a communications network wherein at times there are a large number of packets of information containing a great number of bits being passed in a very short period of time from multiple input ports to multiple output ports, wherein a counter command is modified to reflect subsequent processing of the data packet after the counted event.
BACKGROUND ART
While the invention is not so limited, it is especially useful in communication network systems where large volumes of frames or packets of information are passed from port to port and it is necessary to statistically evaluate the system based on the traffic volume through each port and with the traffic volume between various ports, the number of packets of various sizes of information which are delivered or discarded and other information relating to the operation of the network system. One particular network system of this type is shown and described in U.S. patent application Ser. No. 09/544,896, filed Apr. 7, 2000, entitled Network Processor/Software Control Architecture, the contents of which are incorporated herein by reference as if they were fully set forth. In this type of system, data frames are received at one port from an external source such as a computer, processed and delivered from the incoming port to the required destination port. These incoming ports and destination ports may be on the same blades or different blades, and the various statistical information such as that noted above needs to be accumulated. One technique for accumulating the statistical information is to count the number of occurrences of the various events, such as data entry through a specific port, data exit through a specific port, traffic between specific ports, discarded data, the size of the frames, and other characteristics of the data and store each of these counts in some type of memory.
One particular network system for counting and storing the number of occurrences of each of a plurality of events occurring in a processor complex is shown and described in U.S. patent application Ser. No. 09/656,556, filed Sep. 6, 2003, entitled Method and Structure For Managing Large Counter Arrays, the contents of which are incorporated herein by reference as if they were fully set forth. The structure includes multiple storage devices, each of which includes a plurality of arrays of memory storage for storing count information of each event, which arrays are divided into a plurality of separately addressable groups of memory addresses in each memory array. At least one counter element is associated with each array of memory. A table is provided which contains information, including a point of reference in each array to uniquely define the structure and location of each memory array. At least one processor generates a plurality of parameters for each of the events to uniquely identify the event. A counter manager is provided which communicates with said at least one processor through its associated coprocessors and receives the parameters of each event generated from the at least one processor. The counter manager, utilizing the table and the parameters information from the at least one processor determines the unique physical address location associated with the event, reads the data from the unique address, modifies the read data according to the instructions and writes the modified data to the determined address. The invention also contemplates reading the information, which has been stored in the address without modifying the stored information for statistical evaluation.
Prior art techniques for counting an event are typically implemented as a hardware device that reads a data packet from a location in a memory device, increments the value read, and then write the incremented value back to the same memory address. The prior art methods and structures for storing such information cannot adjust the counting function after the associated data packet has been processed, such as when hardware discards a packet rather than forwards it due to system resource limitations, and the prior art therefore accept counts which are inaccurate. In a multi-processor environment, multiple processors may attempt to increment the same counter, and when this happens the prior art system must grant access to the memory location to only one processor while blocking access by any other processor, until the accessing processor has made its modification and written the modified value back. What is needed is a method and structure for delaying the increment of the counter until a later action determines the proper processing of the counter instruction. What is also needed is a method and structure for delayed increment of a counter in a multiprocessor environment.
SUMMARY OF THE INVENTION
A method and structure for performing a delayed counter increment is provided. In a preferred embodiment, a network processor creates a counter command associated with a data packet based upon examination of the data packet as it is processed through the network system. Subsequent to the generation of the counter command, the counter command may require updating: for example, the data packet may be discarded by hardware instead of forwarded. Therefore, the counter increment instruction must be changed. According to the present invention, a delayed counter increment will perform the actual counter update after the processing of the data packet by hardware. The counter update action is modified depending upon whether the data packet is forwarded or discarded: one counter is selected to be updated if the data packet is forwarded, and a different counter is selected to be updated if the data packet is discarded. This solves a problem that sometimes the forwarding code is unable to determine if some independent action may later discard a data packet.
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Bass Brian Mitchell
Davis Gordon Taylor
Heddes Marco C.
Driggs, Lucas, Brubaker & Hogg
International Business Machines - Corporation
Nieves Michael
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