System for delaying propagation of wake-up signal to processor t

Details System for delaying propagation of wake-up signal to processor t System for delaying propagation of wake-up signal to processor t

1998-01-17

2000-10-03

An, Meng-Al T.

Electrical computers and digital processing systems: support

Computer power control

Power sequencing

713300, C06F 132

Patent

active

061287474

ABSTRACT:
An electronic device such as a computer, is provided with a processor responsive to a sleep signal being asserted to emit a sleep acknowledgement signal and enter a low power mode, and a memory which is also settable in a low power mode. The memory is, for example, a DRAM with a self refresh mode. Control of entry of the memory into its low power (or sleep) mode is effected by a sleep control circuit. This circuit sets the memory into its low power mode upon detection of the sleep acknowledgement signal emitted by the processor. Preferably, the sleep control circuit forms part of a memory controller, and the sleep acknowledgement signal is a bus transaction, that is detected by the memory controller.

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