System for delay reduction during technology mapping in FPGA

Details System for delay reduction during technology mapping in FPGA System for delay reduction during technology mapping in FPGA

2004-12-30

2008-09-30

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07430726

ABSTRACT:
The present invention relates to a system for reducing the delay during technology mapping in FPGA that comprises locating and replicating the critical fan-in nodes in the mapping logic. Parallel computation is performed on the replicated nodes followed by selection of the output. The delay reduction approach in the present invention gives a highly efficient logic implementation when delay is the prime concern and area can be afforded to be expanded. The technique relies on replicating logic and performing parallel computation on delay critical LUT's.

REFERENCES:
patent: 6546539 (2003-04-01), Lu et al.
patent: 6557144 (2003-04-01), Lu et al.
patent: 7219048 (2007-05-01), Xu
patent: 7257800 (2007-08-01), Singh et al.
K.N.Chen et al., “A New Strategy of Performance-Directed Technology Mapping Algorithm for LUT-Based FPGAs,” 1996 IEEE Int'l Symposium on Circuits and Systems, pp. 822-825.
R.J.Francis et al., Technology Mapping of Lookup Table-Based FPGAs for Performance, 1991 IEEE Int'l Conference on CAD, pp. 568-571.

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